Voltage Regulator Architecture for NOR Flash Memory Stability
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Solution Overview
Problem
In semiconductor devices, particularly in NOR flash memory using the Multi Level Cell (MLC) scheme, it is challenging to maintain the necessary voltage relationships between the well voltage and source voltage during read and write operations to prevent potential reversals that can lead to device failure, especially when transitioning between reading and writing states.
Innovation Solution
The implementation of multiple voltage regulators, where a first voltage regulator increases the well voltage and a second voltage regulator increases the word line voltage in response to a trim signal, with the second regulator switching from sourcing current from the first regulator to a power supply line during the pull-up time interval, ensuring a relationship of 'well voltage >= word line voltage' is maintained, thereby preventing potential reversals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the well voltage and source voltage are separated to minimize the capacity driven with the source voltage, then the driving speed is sped up, but the potential relationship of Vwell≥Vwl must be maintained to suppress current in the pn direction
Solution Approach 1:
The word line decoder is designed with preliminary voltage separation where the well voltage and source voltage are decoupled before the switching operation. This allows the source voltage to be rapidly switched without being constrained by the well voltage charging time, while still maintaining the required potential relationship through proper circuit design that prevents current flow in the pn direction.
2Loss of time
If the well voltage is controlled with a certain value and only the source voltage is changed, then the operation time is shortened, but the source voltage has small driving capacity
Solution Approach 1:
The voltage control function is segmented into two independent parts: the well voltage is controlled by a dedicated well voltage controller that maintains a stable reference potential, while the source voltage is controlled by a separate source voltage controller that provides rapid switching capability. This segmentation allows each controller to be optimized for its specific function without compromise.
3Speed
If multiple voltage regulators are used to generate boosted voltages, then the voltage shifting speed is increased, but the device complexity increases
Solution Approach 1:
The first and second voltage regulators are merged into a single integrated word line decoder circuit. The first voltage regulator generates the well voltage and the second voltage regulator generates the source voltage, both within the same decoder block. This integration reduces overall device complexity while maintaining the high-speed voltage shifting capability provided by the dual regulator architecture.
Data Source
AI summary
Integrated circuit memory devices include multiple voltage regulators configured to generate respective boosted voltages, which are provided to a memory cell block. A first voltage regulator is configured to increase a well voltage (Vwell) from a first level to an elevated second level during a pull-up time interval when a boosted well voltage level is required within a memory cell block. The increase in the level of the well voltage occurs in response to a transition of a trim signal (Trim) received at an input of the first voltage regulator. A second voltage regulator is also provided. The second voltage regulator is configured to increase a word line voltage (Vwl) from a third level to an elevated fourth level during the pull-up time interval, in response to the transition of the trim signal and in response to the well voltage. A memory cell block is provided, which is configured to receive the well voltage and the word line voltage during the pull-up time interval.