3D Memory Depletion Region Control for Erase Efficiency
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Solution Overview
Problem
Three-dimensional memory devices face challenges in effectively controlling depletion regions during the erase process, leading to inefficiencies in gate-induced leakage current generation.
Innovation Solution
The implementation of a three-dimensional memory device design with a NAND string structure that includes a semiconductor material stack with source and drain regions, a memory film, and a control circuit to apply specific bias voltages, creating accumulation, inversion, and depletion regions to manage gate-induced leakage current during the erase operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase operations are used in three-dimensional memory devices, then the erase process can be performed, but the depletion region control is insufficient leading to poor gate-induced leakage current generation
Solution Approach 1:
The patent divides the select gate into multiple subsets (first source-side subset, second source-side subset, first drain-side subset, second drain-side subset) that can be independently controlled. This segmentation allows different bias voltages to be applied to different regions, enabling precise depletion region control at specific locations along the NAND string to enhance gate-induced leakage current generation during erase operations.
Solution Approach 2:
The patent applies different bias voltages to different subsets of select gates to create localized depletion regions with specific properties. By making the second source-side subset more negative than the first source-side subset, and similarly for drain-side subsets, the patent creates optimized local electric fields that enhance leakage current generation at critical regions while maintaining overall erase effectiveness.
2Reliability
If multiple bias voltages are applied to control depletion regions, then gate-induced leakage current generation is enhanced, but the device complexity increases
Solution Approach 1:
The patent implements dynamic voltage control where the select gate subsets can switch between different bias states depending on the operational mode (erase vs. program). During erase operations, the control circuit applies specific negative biases to create depletion regions, while during program operations, different voltages are applied. This dynamic adaptability allows the same structure to serve multiple functions without requiring permanently complex circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the control over gate-induced leakage current, improving the efficiency and effectiveness of the erase process in three-dimensional memory devices.
Implementation Method 1
the first source-select-gate bias voltage has a magnitude and a polarity that generate an accumulation region at an intermediate portion of the source region
Implementation Method 2
the second source-select-gate bias voltage has a magnitude and a polarity that generate an inversion region at an upper end portion of the source region
Implementation Method 3
generate a depletion region between the inversion region and the accumulation region
Implementation Method 4
the first drain-select-gate bias voltage has a magnitude and a polarity that generate an accumulation region at an intermediate portion of the drain region
Implementation Method 5
the second drain-select-gate bias voltage has a magnitude and a polarity that generate an inversion region at a lower end portion of the drain region
Implementation Method 6
generate a depletion region between the inversion region and the accumulation region
Data Source
AI summary
Gate-induced leakage current that is independent of a location of a physical p-n junction between a semiconductor channel and a source/drain region can be provided within a NAND string of a three-dimensional memory device by employing at least one leakage current control circuit that is activated during an erase operation. During the erase operation, an accumulation region and an inversion region can be formed between a vertically-neighboring pair of electrically conductive layers with a depletion region therebetween. The depletion region can generate and inject majority charge carriers into the semiconductor channel during the erase operation. The depletion region can be formed in the source region or in the drain region and may not overlap with a physical p-n junction. Thus, the charge injection location can be independent of the location of the physical p-n junction.