3D Vertical Memory Dice Interconnect Optimization

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Solution Overview

Problem

Integrated three-dimensional vertical memory (3D-MV) designs face challenges in cost, performance, and size due to the need for expensive BEOL manufacturing processes and high-temperature interconnect materials, which compromise the peripheral circuit's efficiency and increase overall costs.

Innovation Solution

A discrete 3D-MV design separates the 3D circuit and 2D peripheral circuit into different dice, allowing for optimized BEOL structures, reduced wafer costs, and the use of high-speed interconnect materials, resulting in lower overall costs, improved performance, and smaller size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If integrated 3D-MV design is used, then memory density is improved, but manufacturing cost increases and peripheral circuit performance deteriorates

Engineering Contradiction:

Improvememory densityVSAvoidmanufacturing cost

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent divides the 3D-MV system into separate memory die and peripheral circuit die, allowing independent optimization of each component. The memory die focuses on high-density storage while the peripheral die handles circuit functions, resolving the contradiction between integration benefits and manufacturing costs.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary packaging structure that couples multiple dice together, enabling the separation of memory and peripheral circuits while maintaining system integration. This mediator allows cost-effective manufacturing of individual dice while achieving functional integration at the package level.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Stability of the object's composition

If high-temperature interconnect materials are used in integrated design, then thermal stability is improved, but peripheral circuit speed decreases

Engineering Contradiction:

Improvethermal stabilityVSAvoidperipheral circuit speed

Core Design Contradiction:

Stability of the object's compositionVSSpeed

Solution Approach 1:

The patent applies different interconnect material qualities to different locations: high-temperature stable materials in the memory die where thermal stability is critical, and high-speed materials in the peripheral circuit die where speed is prioritized. This local differentiation resolves the speed-stability contradiction.

Inventive Principle:

Principle #3Local quality

3Productivity

If BEOL manufacturing process is optimized for memory array, then memory performance is improved, but peripheral circuit efficiency decreases

Engineering Contradiction:

Improvememory performanceVSAvoidperipheral circuit efficiency

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The patent segments the backend-of-line (BEOL) manufacturing processes into separate optimization paths: one for the memory array die focusing on high-density interconnects, and another for the peripheral circuit die focusing on high-speed signal routing. This allows each die to achieve optimal performance for its specific function.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9559082B2Three-dimensional vertical memory comprising dice with different interconnect levels

Publication Date: 2017.01.31 HANGZHOU HAICUN INFORMATION TECHNOLOGY CO LTD

AI summary

The present invention discloses a three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. The number of interconnect levels in the peripheral-circuit die is more than the number of interconnect levels in the 3D-array die, but substantially less than the number of memory cells on each of the vertical memory strings in the 3D-array die.