3D Memory Device Using Dielectric Fillers to Space Conductive Layers
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Solution Overview
Problem
Current 3D memory devices face challenges in achieving higher storage capacity within a smaller form factor without compromising operation performance, particularly in integrating stacked memory cells effectively.
Innovation Solution
A three-dimensional memory device is fabricated using a multi-layer stacked structure with conductive and insulating layers, featuring memory layer stacks with string portions and an isolation portion, and additional holes for gate replacement and dielectric filler deposition to enhance storage density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If critical dimensions of devices are shrunk to achieve greater storage capacity within smaller memory device, then storage density is improved, but operation performance deteriorates
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional stacked architecture with vertical channels extending through multiple layers. Memory cells are arranged in stacks with conductive layers and insulating layers alternately stacked, creating vertical memory strings that increase storage capacity without reducing cell dimensions, thus maintaining operation performance while achieving higher density
2Quantity of substance
If stacked multiple planes of memory cells are implemented to increase storage density, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The memory device is segmented into multiple functional layers including conductive layers, insulating layers, and memory layer stacks arranged in a systematic alternating pattern. Each layer performs a specific function, and the segmented structure allows for modular fabrication and assembly, managing complexity through organized division of functional elements
Solution Approach 2:
The patent implements nested structures where memory layer stacks containing channel layers and storage layers are positioned within first holes formed in the alternating conductive and insulating layers. Second holes are then formed between adjacent first holes, creating a nested hierarchical arrangement that increases storage density while maintaining structural organization
Data Source
AI summary
A three-dimensional memory device includes a substrate, a plurality of conductive layers and insulating layers, a memory layer stack, an isolation portion, a second hole and a dielectric filler. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The multi-layer stacked structure includes multiple first holes, and each first hole passing through the conductive layers and the insulating layers. The memory layer stack has a first string portion, a second string portion and a bottom string portion connected between the first and second string portions. The isolation portion is embedded among the first, second and bottom string portions of each of the memory layer stacks in the first holes. The dielectric filler is located on the isolation portion and has side protrusions in contact with the conductive layers.