3D Memory Isolation Structure With Meandering Dielectric Layout

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Solution Overview

Problem

Current three-dimensional memory devices face challenges in efficiently integrating support circuitry for vertical NAND strings, particularly in forming effective dielectric isolation structures that enable stable and efficient operation of memory elements.

Innovation Solution

A semiconductor structure is developed with a meandering dielectric isolation structure, comprising an alternating stack of insulating and electrically conductive layers, memory openings, and dielectric barrier structures, along with conductive via portions to facilitate electrical contact and isolation, allowing for the formation of vertical stacks of memory elements and semiconductor channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional dielectric isolation structures are used in three-dimensional memory devices, then manufacturing processes are simpler, but electrical isolation efficiency and operational stability are insufficient

Engineering Contradiction:
Improveoperational stabilityVSAvoidisolation structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dielectric isolation structure is segmented into multiple portions arranged in a meandering pattern, creating multiple isolation regions that collectively provide enhanced electrical isolation. This segmentation allows the isolation function to be distributed across multiple smaller elements rather than relying on a single continuous structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dielectric isolation structure employs a meandering (curved) geometry instead of straight lines, creating a serpentine pattern that increases the isolation path length within a compact area. This curved configuration enhances electrical isolation efficiency by extending the isolation distance without proportionally increasing the footprint area.

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Reliability

If dielectric material plates are placed at levels of electrically conductive layers, then electrical isolation is improved, but manufacturing complexity increases due to precise alignment requirements

Engineering Contradiction:
Improveelectrical isolationVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

A dielectric barrier structure is introduced as an intermediary element positioned between the dielectric material plates and the electrically conductive layers. This barrier structure facilitates precise alignment and positioning of the dielectric material plates relative to the conductive layers, reducing the direct alignment precision requirements while maintaining effective electrical isolation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If vertical contact via structures are formed through dielectric material plates, then electrical contact efficiency is improved, but device complexity increases due to additional structure layers

Engineering Contradiction:
Improvecontact efficiencyVSAvoidstructure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The vertical contact via structures serve multiple functions: they provide electrical contact through the dielectric material plates, maintain structural integrity across different layers, and enable interconnection between various functional elements. This multi-functionality reduces the need for separate specialized structures, effectively managing complexity while maintaining high contact efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240179904A1Stairless three-dimensional memory device containing meandering dielectric isolation structure and methods of forming the same
Publication Date: 2024.05.30 SANDISK TECHNOLOGIES LLC
  • US20240179904A1 patent drawing
  • US20240179904A1 patent drawing
  • US20240179904A1 patent drawing

AI summary

A method includes forming an in-process alternating stack of insulating layers and sacrificial material layers, forming a meandering dielectric isolation structure through the in-process alternating stack, forming memory stack structures through the alternating stack, where each of the memory stack structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, forming sacrificial via fill structures on the respective sacrificial material layers, replacing first portions of the sacrificial material layers with electrically conductive layers, and forming layer contact via structures contacting a respective one of the electrically conductive layers by replacing at least the sacrificial via fill structures with a conductive material portion.