3D Semiconductor Memory Device With Dielectric Isolation Between Common Source Plugs
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Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in integration due to the high cost and complexity of processing equipment required for fine pattern formation, which hinders increased reliability and integration.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a substrate with alternating stack structures, common source plugs, and vertical dielectric structures, allowing for increased integration and reliability by optimizing the arrangement of insulation layers and electrodes, and using dielectric patterns to enhance channel structures and contact plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor memory devices are used, then manufacturing process is simpler, but integration is limited due to high cost and complexity of processing equipment required for fine pattern formation
Solution Approach 1:
The patent transitions from two-dimensional planar memory devices to three-dimensional vertically stacked memory devices. By stacking multiple memory cell layers vertically, the device achieves higher integration density without requiring finer lateral patterning, thus avoiding the need for expensive advanced lithography equipment while maintaining manufacturing feasibility.
2Quantity of substance
If three-dimensional vertically arranged memory cells are implemented, then integration is increased, but device structure becomes more complex
Solution Approach 1:
The three-dimensional memory device is segmented into multiple identical stack structures, each containing repeating patterns of insulation layers and electrodes. This modular segmentation allows complex 3D functionality to be achieved through repeated simple units, simplifying the overall device design and manufacturing process while maintaining high integration density.
Solution Approach 2:
The patent implements nested stacking where multiple layers of memory cells are vertically arranged with insulation layers and electrodes nested within each other. Each stack structure contains alternating layers that are nested in a systematic pattern, allowing high integration density to be achieved through compact vertical arrangement rather than complex lateral structures.
3Reliability
If multiple common source plugs are placed between stack structures, then electrical connection is improved, but risk of voltage differences and potential failures increases
Solution Approach 1:
A dielectric structure is introduced as an intermediary element between the first and second common source plugs. This dielectric structure electrically isolates the two plugs, preventing harmful voltage differences and potential failures while maintaining reliable electrical connections to the respective stack structures. The dielectric acts as a mediator that enables safe coexistence of multiple common source plugs.
Data Source
AI summary
Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.