Solid-State Devices TRIZ Cases

A semiconductor device design featuring groove-shaped recesses that allow semiconductor layers to overlap source bus lines.

A silicon photomultiplier sensor incorporates a dummy pixel to absorb excess carriers, reducing noise under high-intensity light.

Stacking gate structures and insulating interlayer patterns reduces opening difficulty, enabling high integration degree in memory devices.

Liquid crystal lens arrays refract collimated light beams at adjustable angles to create virtual images with variable spatial depth.

A semiconductor trench fabrication method uses photoresist spacers as etch masks to define precise feature dimensions in dielectric layers.

An organometallic compound uses selenium-linked ligands to stabilize dipole moments and lower HOMO energy levels.

Vertical cross array RRAM cells utilize non-linear resistance for self-gating, eliminating crosstalk and misreading while enabling high-density 3D storage.

An insulation isolation layer between the OLED anode and reflective layer prevents hill lock formation, ensuring high reliability without short circuits.

An elliptical annular jig constrains adhesive tape expansion to equalize spacing between rectangular semiconductor devices.

Dummy electrodes and a getter layer trap mobile ions to prevent defects like wide column gaps in organic electronic devices.

Segmented chambers and thin film insulation maintain thermal energy density, preventing baseline drift in metal oxide gas sensors.

Segmenting the insulating member stabilizes chromaticity by confining fluorescent material, resolving viscosity-induced color variation.

Plasma-oxidized indium oxide replaces separate layers to eliminate etching steps and prevent defective adhesion in GaN LED manufacturing.

Hydrophilic and hydrophobic banks confine organic emission materials, preventing thickness deviations that cause dark points in displays.

Thermal bonding replaces complex electroplating to form metal bumps, reducing manufacturing costs while maintaining connection reliability.

Segmenting select and cell transistors in a vertical pillar structure reduces voltage drop while increasing integration density.

Lateral ground select transistors reduce series resistance in 3D NAND devices by adjusting doping concentrations.

Multi-layer structure combines phase change film with low-resistance conduction layer to enable easy formation of memory elements.

Unaligned drain through-holes in the array substrate minimize overlap with photo spacers, preventing light leakage from uneven support surfaces.

Cyclic platinum and palladium complexes resolve processing difficulties and intermolecular interactions to deliver high color purity and operational stability.

Convex channel areas in a PMOS transistor extend the effective gate length, reducing off-current leakage caused by hot electron punch-through.

Interposers relocate bond pads to resolve connectivity bottlenecks caused by limited surface area in stacked semiconductor packages.

A parallelogram-shaped optoelectronic semiconductor chip expands the radiation exit surface area through asymmetric geometric design.

Segmenting the LED and quantum dot layers avoids indium doping issues, improving efficiency and uniformity across micro-LED arrays.

Asymmetric magnet placement on a single wafer reduces offset field errors from assembly variations while maintaining high measurement precision.

Vapor deposition of DBEDOT monomer eliminates shadow masks by enabling selective polymerization on ITO regions, reducing manufacturing complexity.

Capacitor coupling converts negative potentials to positive signals, enabling accurate comparison and stable holding while reducing leakage current.

A thin-film transistor mask uses a light-adjusting pattern to define precise channel dimensions.

A monolithic imaging device array uses protruding reflective surfaces to guide light through a single molded body.

Segmenting unit pixels into six sub-pixels maintains color reproducibility while increasing display luminance.

A flexible digital X-ray detector panel uses an alternating silicon oxide and nitride buffer stack to reduce device deterioration.

Nanoparticles enable ambient operation and CMOS compatibility by resolving oxygen interference with filament formation.

Trench regions formed using insulating film lines as etching masks prevent charge trapping and simplify fabrication for denser memory arrays.

A pixel structure uses a dielectric layer with island structures to modulate electric fields and enhance liquid crystal efficiency.

Dual organic peroxide initiators in the adhesive layers accelerate curing at 130°C, resolving insufficient adhesive strength during fast compression cycles.

Standardizing trench depth in the patterned passivation layer compensates for non-uniform brightness caused by pozidriv patterns, enhancing transmittance.

Varying grid line widths according to chief ray angle minimizes optical crosstalk and shading variations across the pixel array.

Segmenting the OLED cathode layer creates gaps that allow electric field lines to pass through, resolving shielding issues in on-cell touch designs.

A quantum dot film uses layers with ascending refractive indices to redirect backward light forward through total internal reflection.

A light emitting diode uses a semiconductor carbon nanotube layer as the N-type and active region.

Dual-path current sensing establishes read margins for MRAM by compensating for MTJ resistance variations without increasing power consumption.

Stacked transparent conductive and opaque metal layers form pixel electrodes with line-widths under 3.5 micrometers.

Silicidation reduces gate line resistance while selective etching creates air gaps to minimize parasitic capacitance between floating gates.

A light guide structure redirects front-emitted OLED light through the transparent region to solve unidirectional display limitations.

Merges a Schottky select device with a storage element to limit current flow into unselected word lines, reducing read disturbance in cross-point architectures.

Segmented doped regions isolate high voltage leakage from low voltage circuits, maintaining electrical efficiency during device shrinkage.

Concentric deep trench moats with N+ epitaxial regions attenuate electrical noise coupling to sensitive analog circuits.

Vertical dielectric structures isolate adjacent common source plugs in a 3D semiconductor memory device, preventing voltage differences between stack regions.

A tunnel oxide layer limits current flow through a resistive switching memory element, resolving cross-talk and sensing issues during scaling.

A display substrate replaces traditional color filters with red and green quantum dot emission units alongside a blue-light transmission unit.

Stacked NAND memory employs assist gates to control channel ridges, doubling bit density while reducing off-current leakage and manufacturing complexity.

A resistive coupling structure between circuit environments delays voltage transitions, preventing gate oxide damage during CDM tests.

Segmenting the vertical channel into cylindrical, neck, and base portions improves contact reliability without increasing manufacturing precision requirements.

Composite mask layers enable simultaneous etching of laminated structures, reducing process complexity and step count for 3D NAND fabrication.

A charging circuit assists pre-charging the reference cell data line to reduce read latency.

Segmented inorganic layers with elevated spacing areas absorb bending stress to prevent signal line breakage.

A thin film transistor substrate uses an alkaline developer to pattern metal films while preserving the oxide semiconductor layer.

Multiple EL layers separated by charge-generation layers reduce power consumption while maintaining high luminous efficiency.

A multilayer encapsulation film uses a low-modulus crack barrier to protect organic electronic devices from external environmental factors.

Multi-tone photomasks reduce photolithography steps from six to four, lowering manufacturing costs and improving yield.

A crack detection line with distinct height portions overlaps insulative step portions in the non-display area of a flexible display substrate.

Dual blue LED chips with shifted peak wavelengths reduce harmful radiation while maintaining display brightness and color quality.

An uneven under layer forces connection wiring to turn in thickness directions, reducing planar area while maintaining bending resistance.

Segmenting the buffer layer into organic and inorganic sub-layers reduces dark current caused by impurities while maintaining high external quantum efficiency.

Composite carbon nanotube and silicon oxide matrix reduces power consumption by controlling cell current flow while maintaining high resistance ratio.

Deep trench isolation segments the epitaxial layer to enable high breakdown voltage operation while maintaining standard CMOS gate compatibility.

Applying a sealant layer to the uneven non-display region absorbs mechanical stress and prevents film de-lamination during manufacturing.

A fluoride phosphor AxMFy:Mnz4+ emits red light via photoluminescence.

A fingerprint identification method determines an illuminating region based on a finger pressing area to reduce power consumption.

A single exposure patterning process forms interlevel vias and storage element trenches concurrently within one metal layer.

Pressure-applied protective films enter substrate recesses to prevent adhesive contamination and mechanical damage during processing.

A curable polysiloxane composition cures into an optical encapsulant maintaining refractive index and hardness.

A semiconductor device uses stress to form local gaps in the adhesive layer between structural members.

Conductive particles dispersed in resin form a threshold-switching path between electrodes, preventing ESD damage without absorbing light.

A lighting device incorporates a slit in the metal substrate to reduce solder stress caused by thermal expansion differences, enhancing reliability.

Asymmetrical spacing between composite conductive layers compensates for over-etching to prevent breakage and impedance mismatch in display panels.

Vertical stacking of submounts reduces the package area while maintaining electrical connection reliability and thermal conductivity for mobile applications.

Vertical adhesive pressure bonding joins display and circuit substrates, eliminating FPCB bending stress that causes pad damage.

Protruding heat dissipation terminals on the substrate rear surface resolve the contradiction between compact device size and thermal management performance.

A carbon nanotube film structure heats organic light emitting material to gasify it for deposition on a substrate.

Cluster ion irradiation forms a modifying layer on semiconductor wafers to enable epitaxial growth without recovery heat treatment.

An atomic layer deposited aluminum oxide barrier film prevents hydrogen and water diffusion into the ferroelectric layer, eliminating liner oxide requirements.

A solid-state light-emitting element uses a low refractive index hemispherical lens and planarizing bonding layer to extract light efficiently.

Pre-thinning the capping wafer on a handle substrate avoids mechanical shock defects during bonding.

Segmented capacitor structure isolates defective sub-capacitors via laser cutting of non-overlapping connection portions.

Differentiated hole injection layers for RGB sub-pixels enhance emission luminance and light extraction efficiency while extending element life.

A temporary layer with an undercut structure guides inorganic material deposition to form precise open regions for high-resolution pixel electrodes.

Partition pipe gates segment trench spaces to resolve the contradiction between high integration density and complex manufacturing processes.

Control circuitry detects radiation charge on an interconnect to trigger image acquisition in dental radiography sensors.

A spacer element spaces the convertible structure between electrodes to define the phase change memory cell geometry.

An auxiliary diode layer with a distinct work function stabilizes the Schottky junction interface on metal word lines.

A tapered memory material element concentrates the phase change region, reducing reset current and improving uniformity without sub-lithographic manufacturing.

A lens assembly uses a spacer structure to align optical layers without adhesives.

Stacked second and third metal layers with insulation cushion folding stress to prevent signal line rupture and display errors in the bending region.

Segmenting memory blocks with local data lines reduces parasitic capacitance, lowering the time constant between sense amplifiers and cells.

Curved OLED pixel electrodes reshape optical interference to widen the viewing angle and stabilize light color uniformity against microcavity effects.

A gate contact method positions connections over diffusion regions using controlled etching depths to prevent short circuits.

A stacked LED structure uses a conductive contact zone to connect active layers in series, enabling efficient charge carrier transfer.

A memory device sequencer adjusts control voltage to transfer transistors based on program loop counts.