SPAD Isolation on SOI Substrate for CMOS Compatibility
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Solution Overview
Problem
Existing single photon avalanche diodes (SPADs) integrated with CMOS circuits face challenges due to incompatibility of high breakdown voltages with standard CMOS transistor gates, leading to inability to turn off the SPAD and present a load, affecting sensitivity and operational efficiency.
Innovation Solution
A substrate isolated SPAD is implemented using a silicon on insulator substrate with deep trench isolation and a multiplexer circuit to control bias voltage, allowing selective on/off operation and compatibility with CMOS gates by using a quench resistor and AC coupling capacitor to manage reverse bias and prevent current draw during non-operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SPAD is integrated with CMOS circuits using high breakdown voltage, then the SPAD detection function is achieved, but the high voltage is incompatible with standard CMOS transistor gates causing inability to turn off the SPAD
Solution Approach 1:
The patent segments the substrate into isolated regions using deep trench isolation structures. Each SPAD device is electrically isolated in its own region, allowing independent voltage control and turning off of individual devices without affecting the entire CMOS circuit. This segmentation enables the high voltage SPAD to coexist with standard CMOS gates by preventing electrical interference and allowing separate bias control.
Solution Approach 2:
The patent introduces deep trench isolation structures filled with dielectric material as an intermediary between the high voltage SPAD region and the standard CMOS circuit region. This intermediary structure provides electrical isolation while maintaining physical integration, allowing the high breakdown voltage to be applied to the SPAD without directly affecting the CMOS transistor gates, thus enabling both high voltage operation and CMOS compatibility.
2Measurement precision
If the SPAD remains continuously on to maintain detection capability, then sensitivity is maintained, but power consumption increases due to continuous current draw
Solution Approach 1:
The patent implements dynamic control of the SPAD bias voltage through separate control terminals. The SPAD can be dynamically switched between an active state (with reverse bias for high sensitivity) and an inactive state (with zero or forward bias to stop current draw). This dynamic voltage control allows the system to optimize between sensitivity and power consumption based on operational requirements, turning the SPAD off when detection is not needed while maintaining it when detection is required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the SPAD to be turned off selectively, reducing power consumption and improving compatibility with CMOS circuits, enhancing sensitivity and operational efficiency by controlling the reverse bias and preventing current draw during non-operation.
Implementation Method 1
a deep trench isolation penetrating completely through the epitaxial semiconductor layer to the buried insulating layer, said deep trench isolation electrically insulating a first region of the epitaxial semiconductor layer from a second region of the epitaxial semiconductor layer
Implementation Method 2
a multiplication junction 130, where avalanche breakdown occurs during use, that is located at the PN junction between the p-type doped epitaxial semiconductor layer 102 and the n-type doped deep well 110
Data Source
AI summary
A semiconductor on insulator substrate includes a semiconductor support layer, a buried insulating layer over the semiconductor support layer and an epitaxial semiconductor layer over the buried insulating layer. A deep trench isolation penetrates completely through the epitaxial semiconductor layer to the buried insulating layer to electrically insulate a first region of the epitaxial semiconductor layer from a second region of the epitaxial semiconductor layer. A single photon avalanche diode (SPAD) includes an anode formed by the first region of the epitaxial semiconductor layer and a cathode formed by a well located within the first region of the epitaxial semiconductor layer. An ancillary circuit for the SPAD is located in the second region of the epitaxial semiconductor layer and electrically coupled to the SPAD.