Tapered Memory Element for Phase Change Reset Current Reduction
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Solution Overview
Problem
Existing phase change memory devices face limitations in reducing the reset current required for transitioning from a crystalline to an amorphous state due to the volume of phase change material that needs to change phase, which is constrained by standard integrated circuit manufacturing processes and results in non-uniformity and reliability issues in high-density memory devices.
Innovation Solution
A memory cell structure is developed with a memory material structure comprising upper and lower memory material portions and a memory material element, where the memory material element has a minimum lateral dimension significantly smaller than the average, and a tapered shape to concentrate the phase change region, reducing the reset current requirement by using a lower memory material layer as a thermal barrier between the memory material element and the bottom electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the size of the phase change material element is reduced to minimize reset current, then the reset current magnitude is reduced, but the manufacturing precision and uniformity deteriorate due to limitations of standard integrated circuit manufacturing processes
Solution Approach 1:
The patent transitions from planar 2D memory cell structures to 3D vertically-stacked structures with multiple memory material layers separated by intervening layers. This dimensional change allows the phase change material elements to be positioned at different vertical levels, enabling smaller lateral dimensions while maintaining manufacturability through standard processing techniques. The vertical stacking provides additional design space to achieve small feature sizes without being constrained by lithographic resolution limits in the lateral plane.
Solution Approach 2:
The memory structure is divided into multiple discrete memory material layers (first memory material layer, second memory material layer, etc.) separated by intervening layers. Each layer can be independently processed and controlled, allowing the phase change material elements in different layers to have optimized dimensions for minimizing reset current. The segmentation enables each layer to be manufactured with standard processes while achieving overall small feature sizes through the stacked configuration.
2Reliability
If the volume of phase change material is reduced to achieve higher current densities, then the reset current requirement is reduced, but the reliability and uniformity of phase change memory cells deteriorate
Solution Approach 1:
The patent employs composite structures consisting of multiple memory material layers with different compositions or phases. The first memory material layer and second memory material layer can have different material properties, allowing optimization of each layer's volume and composition for reliable phase change operation. The composite structure enables the phase change material volume to be reduced while maintaining uniformity through the distributed configuration across multiple layers, each contributing to the overall reliability of the memory cell.
Solution Approach 2:
By distributing the phase change material volume across multiple vertical layers rather than concentrating it in a single large lateral area, the patent achieves higher current densities in each smaller layer while maintaining overall reliability. The vertical dimension provides additional space to accommodate the necessary phase change material volume without requiring large lateral dimensions, thereby ensuring uniform operation across all memory cells in the array.
3Ease of manufacture
If standard integrated circuit manufacturing processes are used, then the ease of manufacture is maintained, but the minimum feature size is constrained preventing high-density memory implementation
Solution Approach 1:
The patent utilizes vertical stacking of memory material layers to achieve small effective feature sizes without requiring sub-lithographic lateral dimensions. By moving the miniaturization effort into the vertical dimension, the invention maintains compatibility with standard integrated circuit manufacturing processes that can deposit and pattern multiple thin films at controlled thicknesses, while achieving the small feature sizes necessary for high-density memory through the stacked 3D configuration.
Solution Approach 2:
The memory structure is segmented into multiple layers that can be manufactured using standard thin-film deposition and patterning processes. Each layer is processed independently with conventional techniques, maintaining ease of manufacture. The segmentation into stackable units allows the overall device to achieve high density through vertical integration rather than requiring extremely small lateral features that would demand advanced lithography beyond standard manufacturing capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reduction of the reset current needed for phase change memory devices, enhancing the reliability and uniformity of phase change memory cells, enabling the creation of high-density memory devices with smaller feature sizes without requiring sublithographic manufacturing techniques.
Implementation Method 1
Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase.
Implementation Method 2
Current heats the material and causes transitions between the states.
Implementation Method 3
The memory material element electrically connects the upper memory material portion with the lower memory material layer. The memory material element defines an electrical property state change region therein.
Data Source
AI summary
A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions and a memory material element therebetween. The lower memory material layer is in electrical contact with a bottom electrode. The lower memory material layer has an average lateral dimension. The memory material element defines an electrical property state change region therein and has a minimum lateral dimension which is substantially less than the average lateral dimension. In some examples the memory material element is a tapered structure with the electrical property state change region at the junction of the memory material element and the lower memory material layer.