Gate Contact Over Diffusion Region in Integrated Circuits
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Solution Overview
Problem
As integrated circuit geometries shrink, accurately forming non-rectilinear patterns becomes increasingly difficult, leading to alignment issues and reduced circuit density, particularly due to the risk of short circuits when forming gate connections over diffusion regions.
Innovation Solution
The method involves forming local interconnect conductors as separate source and drain electrodes, with etching techniques that ensure the gate opening's maximum depth is insufficient to reach the diffusion region, allowing for more reliable and dense circuit formation using rectilinear shapes, and employing etch stop layers and double-patterning techniques to control etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate opening is aligned over the gate electrode to ensure accurate gate connection, then the alignment precision is improved, but the risk of short circuit increases when misalignment occurs and the etching depth is not controlled
Solution Approach 1:
The gate opening is formed with a maximum depth that is intentionally set to be insufficient to reach the diffusion region, even when misalignment occurs. This preliminary depth limitation prevents short circuits before they can happen, allowing the gate opening to be aligned over the gate electrode for accurate gate connection while maintaining reliability
Solution Approach 2:
The gate opening acts as an intermediary structure that connects the gate connection conductor to the gate electrode without directly exposing the diffusion region. By controlling the etching depth to stop before reaching the diffusion region, the gate opening mediates between the need for accurate alignment and the risk of short circuits
2Reliability
If the gate opening is offset from the diffusion region to prevent short circuits, then the reliability is improved, but the circuit density decreases
Solution Approach 1:
The etching depth of the gate opening is preliminarily controlled to be insufficient to reach the diffusion region. This allows the gate opening to be positioned over the gate electrode (improving density) while the depth control prevents short circuits, eliminating the need to offset the gate opening from the diffusion region
Solution Approach 2:
The maximum etching depth parameter of the gate opening is changed from a value that would reach the diffusion region to a value that stops before reaching it. This parameter change allows the gate opening to be aligned over the gate electrode for higher density while maintaining short circuit prevention through depth control
3Reliability
If the etching depth for source and drain openings is increased to reach the diffusion region, then the electrode connection reliability is improved, but the manufacturing complexity increases due to different etching depths required
Solution Approach 1:
The etching process is segmented into separate steps: first etching the gate opening with a controlled maximum depth that does not reach the diffusion region, then etching the source and drain openings with greater depth to reach the diffusion region. This segmentation allows each opening type to have optimized depth without complicating the overall process
Solution Approach 2:
The gate opening is etched first with a preliminary depth control that stops before reaching the diffusion region. This preliminary action establishes a safe depth baseline, after which source and drain openings can be etched to the required deeper level without risk of short circuits, simplifying the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher circuit densities by reducing the risk of short circuits, allowing for more accurate and reliable manufacturing of rectilinear forms, thereby improving the yield and reducing costs while maintaining circuit functionality.
Implementation Method 1
etching through said upper insulator layer at least one electrode opening reaching an upper surface of one of said local interconnect conductors and a gate opening overlying said diffusion region and reaching at least an upper surface of said gate electrode, etching of said gate opening being such that said gate opening has a maximum depth insufficient to reach said diffusion region
Implementation Method 2
depositing an electrode connection conductor in to each of said at least one electrode opening and a gate connection conductor in to said gate opening
Data Source
AI summary
A method of forming an integrated circuit 68 provides over a diffusion region 28 on a substrate 26 a gate electrode 36. A source electrode is provided by a source local interconnect conductor 30 and a drain electrode is provided by a drain local interconnect conductor 32. An insulator layer 38 is formed over these electrodes and respective electrode openings are formed through the insulator layer 38 so as to provide electrical connection to a Metal1 layer 46, 48, 50. The etching process for the electrode openings is controlled such that the maximum etching depth is insufficient to penetrate through the insulating layer 38 and accordingly short circuit a gate insulator layer 34 provided between the diffusion region 28 and the gate electrode 36. Thus, the gate opening may be positioned over the diffusion region 28. Double patterning followed by separate etching steps for the gate opening and the source/drain opening may be used to control the gate opening depth and permit the gate contact to be position overlying the diffusion region.