Semiconductor Structure for HV-LV Isolation and Leakage Control
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Solution Overview
Problem
Shrinking semiconductor device sizes leads to a dramatic drop in electrical efficiency, and high operating voltage and leakage in HV devices can negatively impact the efficiency of LV devices, necessitating a solution to maintain efficiency without affecting lower voltage devices.
Innovation Solution
A semiconductor structure comprising doped regions with specific conductivity types and gate structures, where the first gate structure is applied with a voltage, and the fourth doped region is coupled to an anode or cathode, while the second and third doped regions are coupled to another electrode, creating an IGBT device with a second gate structure functioning as a DMOS gate to form multiple channels and restrict hole current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the device area is shrunk to improve integration density, then the productivity and cost per integrated circuit unit are improved, but the electrical efficiency of the semiconductor structure drops dramatically
Solution Approach 1:
The semiconductor structure is segmented into distinct HV and LV device regions with separate doped regions (first doped region for HV, second doped region for LV). This segmentation allows each device type to operate independently with optimized electrical characteristics, preventing the HV device's high voltage and leakage from affecting the LV device, thus maintaining overall electrical efficiency while achieving high integration density.
Solution Approach 2:
Different doped regions are assigned specific conductivity types and doping concentrations tailored to local requirements. The first doped region has conductivity type and doping optimized for HV operation, while the second doped region is optimized for LV operation. This local quality differentiation ensures each region performs its function efficiently without compromising the other, resolving the contradiction between device miniaturization and electrical efficiency maintenance.
2Power
If the first doped region operates at high voltage, then the power handling capability is improved, but the high voltage and leakage affect the LV device and reduce operating efficiency
Solution Approach 1:
The harmful high voltage and leakage effects from the HV device are extracted and contained within the first doped region through the use of the second doped region as a隔离 layer. The second doped region, with its specific conductivity type and doping concentration, acts as a barrier that prevents HV-induced substrate current from reaching the LV device, thus extracting the harmful effect from the LV device while preserving the HV device's power handling capability.
Solution Approach 2:
The second doped region serves as an intermediary between the HV and LV devices. With conductivity type opposite to the first doped region and specific doping concentration, it mediates the interaction between HV and LV devices by blocking the flow of harmful substrate current while allowing both devices to coexist on the same substrate. This intermediary structure enables the HV device to operate at high voltage without degrading the LV device's operating efficiency.
3Reliability
If the substrate current is suppressed to protect LV devices, then the reliability is improved, but the device structure becomes more complex
Solution Approach 1:
The substrate current suppression function is merged into the existing doped region structure. The second doped region, which is already necessary for forming the LV device, is designed with specific conductivity type and doping concentration to simultaneously serve as both the LV device active region and the substrate current barrier. This merging approach achieves reliable protection of LV devices from HV-induced substrate current without adding separate complex suppression structures, thus improving reliability while minimizing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor structure effectively prevents hole current from affecting LV devices during high voltage operation, achieving low turn-on voltage and resistance, and suppressing substrate current leakage, thereby maintaining efficiency and preventing punch-through effects.
Implementation Method 1
A first voltage is applied to the first gate structure. The fourth doped region is coupled to a first electrode. The first electrode is one of an anode and a cathode. The second doped region and the third doped region is coupled to a second electrode.
Implementation Method 2
The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity.
Implementation Method 3
The semiconductor structure effectively prevents hole current from affecting LV devices during high voltage operation, achieving low turn-on voltage and resistance, and suppressing substrate current leakage, thereby maintaining efficiency and preventing punch-through effects.
Data Source
AI summary
A semiconductor device and an operating method for the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a first gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity. The first gate structure is on the second doped region. The third doped region and the fourth doped region are in the second doped region and the first doped region on opposing sides of the first gate structure respectively.