Vertical Non-Volatile Memory Pillar Structure Integration Density
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Solution Overview
Problem
Current vertical-type non-volatile memory devices face challenges in increasing integration density and reducing voltage drop due to the presence of charge-trapping layers in transistors, which also lead to crystal defects and operational limitations.
Innovation Solution
A vertical-type non-volatile memory device design that eliminates charge-trapping layers from the ground source and string select transistors, utilizing a pillar-shaped single-crystalline semiconductor pattern with tunnel oxide layers and insulation interlayers to enhance integration density and reduce voltage drop, while forming cell transistors with fewer crystal defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge-trapping layers are formed in all transistors including ground source and string select transistors, then non-volatile memory functionality is achieved, but voltage drop increases and reliability decreases
Solution Approach 1:
The patent applies local quality by differentiating the structure of select transistors from cell transistors. Specifically, the ground source select transistor and string select transistor are configured without charge-trapping layers, while cell transistors retain them. This localized structural differentiation allows select transistors to have lower resistance and reduced voltage drop, while cell transistors maintain non-volatile storage capability through their charge-trapping layers.
Solution Approach 2:
The patent segments the transistor population into two functional groups: select transistors (ground source and string select) that control access and require low resistance, and cell transistors that perform storage and require charge-trapping layers. This segmentation allows optimization of each group's structure according to its specific functional requirements, resolving the contradiction between voltage drop and memory functionality.
2Productivity
If cell transistors are stacked vertically to improve integration density, then degree of integration increases, but crystal defects and manufacturing complexity increase
Solution Approach 1:
The patent transitions from planar transistor arrangement to vertical stacking, utilizing the third dimension to increase integration density. Multiple cell transistors are stacked along the vertical direction, allowing more storage cells to be packed into the same footprint area. This dimensional change enables higher productivity without requiring proportional increases in manufacturing precision for lateral positioning.
Solution Approach 2:
The patent changes the structural parameters of transistors by forming them with pillar-shaped single-crystalline semiconductor patterns instead of planar structures. This parameter change in geometry allows vertical stacking while maintaining crystal quality, as the pillar structure provides better mechanical support and reduces stress-induced defects during the stacking process.
3Reliability
If pillar-shaped single-crystalline semiconductor patterns are used, then cell current and distribution characteristics improve, but manufacturing complexity increases
Solution Approach 1:
The patent changes the geometric parameters of the semiconductor pattern from planar to pillar-shaped structures. This parameter change in shape and dimension improves cell current characteristics and distribution by providing better electrical contact and more uniform current flow paths. The pillar structure also enhances mechanical stability, reducing defect formation during vertical stacking operations.
Data Source
AI summary
In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern.