Semiconductor Memory Cell Miniaturization via Trench Isolation
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Solution Overview
Problem
Conventional semiconductor devices face challenges in miniaturizing memory cells due to charge trapping issues and the complexity of etch processes, particularly in trench portion formation between bit lines and word lines, which hinders downsizing and leads to malfunctioning memory cells.
Innovation Solution
A semiconductor device with a trench region formed between bit lines and word lines, using insulating film lines as etching masks to prevent current flow and charge trapping, allowing for narrower spacing between word lines and simplified etch processes, thereby enabling miniaturization of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trench portion is provided in the semiconductor substrate between bit lines and between word lines to prevent charge trapping, then memory cell reliability is improved, but device complexity increases due to the complexity of the etch process
Solution Approach 1:
The patent applies preliminary action by forming insulating film lines on the bit lines before the etching process. These insulating film lines serve as pre-prepared etching masks that define the trench portions. By having the masks in place beforehand, the subsequent etching process becomes straightforward and selective, eliminating the need for complex multi-step etching procedures while still achieving the desired trench formation for charge isolation.
Solution Approach 2:
The insulating film lines act as an intermediary element between the bit lines and the etching process. Rather than directly etching the substrate with complex masking procedures, the insulating film lines mediate the process by serving as simple etching masks. This intermediary layer simplifies the etching step while ensuring precise trench formation for charge isolation, thus reducing overall process complexity.
2Area of moving object
If the spacing between word lines is reduced to miniaturize memory cells, then memory cell size is reduced, but charge trapping occurs in the ONO film at both sides of the word lines
Solution Approach 1:
The patent applies segmentation by introducing trench portions that divide and isolate the channel regions between adjacent memory cells. These trenches physically segment the substrate, preventing charge from spreading laterally to the ONO film at the sides of word lines. This segmentation allows word lines to be placed closer together without causing charge trapping issues, enabling miniaturization while maintaining reliability.
Solution Approach 2:
The patent extracts or removes the problematic charge flow path by forming trench portions that eliminate the lateral conduction paths in the substrate. By taking out these unwanted current paths through trench formation, charge is confined to the intended channel region beneath the word lines, preventing charge trapping in the ONO film at the sides while allowing reduced word line spacing.
3Manufacturing precision
If conventional etching processes are used to form trench portions, then manufacturing precision is maintained, but device complexity increases due to the need for multiple oxide film layers
Solution Approach 1:
The patent extracts or removes the unnecessary oxide film layers from the conventional structure. Instead of using multiple oxide layers as etching masks, the invention uses only the insulating film lines formed on the bit lines as masks. This simplification reduces device complexity while the self-aligned nature of using the insulating film lines as masks maintains the manufacturing precision required for accurate trench formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively isolates elements between word lines, allowing for the miniaturization of memory cells without bird's beak formation and reducing the complexity of the etch process, thereby enhancing memory cell density and device efficiency.
Implementation Method 1
forming a trench region between the bit lines and between the word lines in the semiconductor substrate. Forming the trench region may include etching the semiconductor substrate by using at least the insulating film lines as an etching mask
Data Source
AI summary
There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), insulating film lines (18) located on the bit lines (14) to successively run in a length direction of the bit lines (14), gate electrodes (16) located above the semiconductor substrate (10) between the bit lines (14), and word lines (20) located on the gate electrodes (16) to run in a width direction of the bit lines (14), a trench region (22) formed between the bit lines (14) and the between word lines (20) in the semiconductor substrate, and there is also provided a fabrication method therefor. According to the present invention, it is possible to provide a semiconductor device where elements can be isolated between the word lines (14) and memory cells can be miniaturized, and to provide a fabrication method therefor.