Chip-Scale Package Vertical Stacking for Edge-Emitting Semiconductor Devices
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Solution Overview
Problem
Conventional chip-on-submount packages for edge-emitting semiconductor devices are relatively large, making them unsuitable for mobile applications where a smaller form factor is required.
Innovation Solution
A chip-scale package design featuring a vertically stacked edge-emitting semiconductor device chip sandwiched between a top submount and a bottom submount, where both submounts are thermally conductive and have a surface area greater than the chip but less than or equal to 1.2 times the chip area, eliminating the need for wire bonds and allowing for smaller package dimensions through a single-step reflow attachment process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional chip-on-submount package is used to provide space for electrical connections during burn-in and testing, then reliable electrical connections are achieved, but the package area becomes relatively large
Solution Approach 1:
The patent transitions from a conventional planar package layout to a three-dimensional stacked configuration where the semiconductor chip is vertically positioned between a top submount and a bottom submount. This vertical stacking enables electrical connections to be established through the thickness dimension rather than requiring extensive lateral space, thereby reducing the package footprint while maintaining connection reliability
Solution Approach 2:
The patent integrates multiple functions into the submount structures. The top and bottom submounts simultaneously serve as mechanical support, thermal management interfaces, and electrical connection points. By merging these functions into compact submount structures with optimized pad layouts, the design achieves reliable electrical connections without requiring a large package area
2Area of stationary object
If the package area is reduced for mobile applications, then smaller form factor is achieved, but space for electrical connections during burn-in and testing becomes insufficient
Solution Approach 1:
The patent utilizes the vertical dimension to accommodate testing and burn-in operations. The exposed top surface of the top submount and the bottom surface of the bottom submount provide accessible areas for probe card contact and electrical connections during testing, eliminating the need for lateral expansion of the package area
Solution Approach 2:
The submount structures are designed with non-uniform pad distributions that concentrate connection areas at the top and bottom surfaces where they are most accessible for testing. This local concentration of electrical connection functionality allows compact overall dimensions while maintaining sufficient test access
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The chip-scale package achieves a smaller form factor, enhancing compatibility with mobile applications by reducing the package area while maintaining reliable electrical connections and thermal conductivity, and allowing for efficient burn-in and testing without direct contact to the chip.
Implementation Method 1
A bottom, p-side surface of the chip is attached and electrically connected to the anode pad with solder, e.g., a gold-tin (AuSn) solder
Implementation Method 2
wire bonds, e.g., gold wire bonds, are used to electrically connect a top, n-side surface of the chip to the cathode pad
Data Source
AI summary
A chip-scale package for an edge-emitting semiconductor device and a semiconductor device assembly including such a chip-scale package are provided. The chip-scale package includes an edge-emitting semiconductor device chip, a top submount disposed on a top surface of the chip, and a bottom submount disposed on a bottom surface of the chip. The top-submount area and the bottom-submount area are each greater than the chip area and less than or equal to about 1.2 times the chip area.