Groove Recess Semiconductor Layers for High-Definition Display TFTs

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-definition display devices face challenges in reducing the area occupied by thin-film transistors (TFTs) without degrading their performance, leading to potential brightness unevenness in light emission surfaces due to close proximity of adjacent TFTs.

Innovation Solution

A semiconductor device design featuring a substrate with groove-shaped recesses that allow semiconductor layers to overlap source bus lines, increasing the distance between adjacent TFTs and maintaining high-definition display quality by preventing aperture ratio reduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the pixel region size is reduced to achieve high-definition display, then the display resolution is improved, but the distance between adjacent TFTs becomes too small causing brightness unevenness

Engineering Contradiction:
Improvedisplay resolutionVSAvoidbrightness unevenness
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a groove-shaped recess structure that extends in the thickness direction (third direction) to create vertical separation between adjacent TFTs. This dimensional change from planar to three-dimensional arrangement allows the TFTs to be physically isolated while maintaining high display resolution, thereby preventing brightness unevenness caused by adjacent TFT interference

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If the TFT occupation area is reduced to fit more pixels, then the pixel density is improved, but the TFT performance deteriorates due to insufficient space

Engineering Contradiction:
Improvepixel densityVSAvoidTFT performance
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

By utilizing the thickness direction through groove-shaped recesses, the patent effectively increases the available space for each TFT without reducing the planar pixel density. The recess structure provides dedicated vertical space for TFT components, ensuring proper electrical connections and performance while maintaining high pixel density in the planar view

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Object-affected harmful factors

If the distance between adjacent TFTs is increased to prevent interference, then the display quality is improved, but the pixel region area increases reducing definition

Engineering Contradiction:
ImproveTFT interferenceVSAvoiddisplay definition
Core Design Contradiction:
Object-affected harmful factorsVSMeasurement precision

Solution Approach 1:

The patent resolves this contradiction by shifting the separation mechanism from the planar dimension to the vertical dimension. The groove-shaped recesses create physical isolation between adjacent TFTs in the thickness direction, preventing interference without requiring increased planar spacing, thus maintaining high display definition

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11550196B2Semiconductor device and display device
Publication Date: 2023.01.10 SHARP KK
  • US11550196B2 patent drawing
  • US11550196B2 patent drawing
  • US11550196B2 patent drawing

AI summary

A display device in the present disclosure includes the following: a substrate; a plurality of source bus lines extending in a first direction above the substrate; a plurality of semiconductor layers extending in the first direction above the plurality of source bus lines; and a first groove-shaped recess extending in a second direction crossing the first direction, the first groove-shaped recess constituting a first contact hole extending from above the plurality of source bus lines to the plurality of source bus lines. Each of the plurality of semiconductor layers is disposed along a surface of the first groove-shaped recess so as to cross the first groove-shaped recess, and each of the plurality of semiconductor layers is electrically connected to each of the plurality of source bus lines on the bottom surface of the first groove-shaped recess.