Trench Gate Semiconductor Memory Integration Density
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in increasing integration density while simplifying the manufacturing process, as existing techniques are complex and inefficient in arranging memory cells and channels effectively.
Innovation Solution
The semiconductor device incorporates a trench structure with multiple pipe gates and channels, where the second pipe channel is shorter than the first, allowing for improved channel area division and integration, and a method of manufacturing involving sacrificial layers and partition pipe gates to simplify the process, enabling efficient formation of memory strings within a limited space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked three-dimensionally to increase integration, then integration density is improved, but manufacturing process complexity increases
Solution Approach 1:
The trench is divided into multiple spaces by partition pipe gates, and each space contains separate pipe channels. This segmentation allows independent formation and control of different channel regions, simplifying the manufacturing process while achieving high integration density through three-dimensional stacking of memory cells.
Solution Approach 2:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking. Memory cells are stacked along the vertical direction within the trench structure, enabling increased integration density by utilizing the third dimension (height) rather than only expanding in the planar area.
2Quantity of substance
If multiple pipe channels are arranged in limited space, then integration density is improved, but channel length uniformity deteriorates
Solution Approach 1:
The trench is segmented into first and second spaces by partition pipe gates, with each space containing pipe channels of controlled lengths. The first pipe channels and second pipe channels can have different lengths optimized for their respective functions, while maintaining uniformity within each group through precise partition placement.
Solution Approach 2:
Different regions of the trench are assigned different channel lengths based on local functional requirements. The first pipe channels in the first space have one length optimized for specific memory cell operations, while the second pipe channels in the second space have a different length optimized for other operations, allowing each region to have the quality needed for its specific function.
Data Source
AI summary
Disclosed is a method of manufacturing a semiconductor device. The semiconductor device may be manufactured by forming a trench extended in a first direction within a first pipe gate, forming a trench filled structure including a first sacrificial layer along a surface of the trench, a second pipe gate along a surface of the first sacrificial layer, and a second sacrificial layer filled in a center area of the trench opened by the second pipe gate inside the trench, and forming a partition pipe gate disposed within the trench in a second direction crossing the first direction to divide the first sacrificial layer into first sacrificial patterns and to divide the second sacrificial layer into second sacrificial patterns.