Semiconductor Gate Line Silicidation and Air Gap Formation
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with gate lines face challenges in reducing the resistance of gate lines while maintaining the integration density, as the width of gate lines is narrowed, leading to increased resistance and interference between floating gates due to parasitic capacitance.
Innovation Solution
A method involving the formation of first and second gate lines at different intervals, followed by etching a multi-layered insulating layer to expose the gate lines and form air gaps, and subsequent silicidation to create metal silicide layers with lower resistance, thereby reducing parasitic capacitance and improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the width of gate lines is narrowed to increase integration density, then the integration density is improved, but the resistance of gate lines increases
Solution Approach 1:
The patent changes the material composition parameter of the gate line by forming a metal silicide layer (such as cobalt silicide, nickel silicide, or tungsten silicide) on the gate line structure. This material transformation reduces the electrical resistance of the narrow gate line while maintaining the high integration density achieved through narrow linewidths.
2Quantity of substance
If the width of gate lines is narrowed to increase integration density, then the integration density is improved, but the parasitic capacitance between floating gates increases
Solution Approach 1:
The patent extracts or removes the multi-layered insulating layer in specific regions between adjacent floating gates through selective etching. By removing portions of the insulating layer, air gaps are formed between the floating gates, which significantly reduces the parasitic capacitance between them while maintaining high integration density.
3Object-generated harmful factors
If a multi-layered insulating layer is etched to form air gaps between gate lines, then the parasitic capacitance is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent forms a sacrificial layer between the floating gates before forming the multi-layered insulating layer. This preliminary action enables selective removal of the insulating layer in subsequent steps by etching through the sacrificial layer, thereby creating air gaps. This approach simplifies the overall manufacturing process compared to direct selective etching of the insulating layer.
Solution Approach 2:
The sacrificial layer acts as an intermediary element that facilitates the formation of air gaps. It is deposited between the floating gates, allows for controlled removal to create voids, and is subsequently eliminated, leaving behind the desired air gap structure that reduces parasitic capacitance.
4Reliability
If metal silicide layer is formed on gate lines to reduce resistance, then the electrical conductivity is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the gate line formation process with the metal silicide layer formation process. The metal silicide layer is deposited conformally over the gate line structure and then selectively removed in regions where it is not needed, combining multiple functions into an integrated process flow that reduces resistance without adding excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively lowers the resistance of gate lines and minimizes interference between floating gates by forming metal silicide layers with low resistance and creating air gaps, enhancing the integration density and performance of semiconductor devices.
Implementation Method 1
forming the exposed parts of the silicon layer into metal silicide layer by a silicidation process
Implementation Method 2
etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and between the first and the second gate lines
Data Source
AI summary
A semiconductor device is manufactured by, inter alia: forming second gate lines, arranged at wider intervals than each of first gate lines and first gate lines, over a semiconductor substrate; forming a multi-layered insulating layer over the entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and the first and the second gate lines; forming mask patterns formed on the respective remaining multi-layered insulating layers and each formed to cover the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first and the second gate lines are exposed.