Multifunction Single Via Patterning for Semiconductor Integration
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Solution Overview
Problem
The existing semiconductor processing techniques face challenges in efficiently integrating energy storage elements, such as memory devices, with vias within the same metal layer, requiring multiple patterning exposure processes and resulting in long vias that complicate the fabrication process.
Innovation Solution
The integration of energy storage elements, like phase change memory (PCM) or resistive random access memory (RRAM) elements, is achieved concurrently with via formation within the same metal layer using a single exposure patterning process, allowing for the formation of interlevel vias that contact the storage elements and metal lines in a single metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning exposure processes are used to integrate energy storage elements with vias, then the integration precision is improved, but the device complexity and fabrication complexity increase
Solution Approach 1:
The patent combines the patterning of energy storage elements and vias into a single exposure process. The resist pattern is formed once, and then trenches for both storage elements and vias are etched simultaneously in the same metal layer, eliminating the need for multiple separate patterning steps while maintaining alignment precision.
Solution Approach 2:
The single exposure process serves multiple functions: it patterns both the energy storage elements and the vias that will contact them, creating a universal patterning step that accomplishes what previously required separate dedicated processes for each structure type.
2Manufacturing precision
If multiple patterning exposure processes are used to integrate energy storage elements with vias, then the integration precision is improved, but the productivity decreases
Solution Approach 1:
The patent merges multiple sequential patterning operations into a single parallel process. By forming all trenches (both for storage elements and vias) in one etching step after a single resist pattern, the manufacturing cycle is shortened and throughput is increased.
Solution Approach 2:
The resist pattern is formed in advance with all necessary features (both storage element trenches and via trenches) defined in a single lithography step. This preliminary action eliminates subsequent alignment and patterning steps, directly improving productivity.
3Reliability
If long vias are used to contact storage elements in different metal layers, then the connectivity is achieved, but the device complexity and fabrication complexity increase
Solution Approach 1:
Instead of using vertical vias extending through multiple metal layers (z-dimension), the patent places both the energy storage elements and their contacting vias within the same metal layer (x-y plane). This dimensional reorganization eliminates the need for long vertical interlayer connections.
Solution Approach 2:
The patent merges the storage element formation and via formation into the same metal layer and the same processing step. The trenches are etched concurrently, and conductive material is deposited in both locations simultaneously, simplifying the fabrication sequence.
Data Source
AI summary
A semiconductor device includes a plurality of storage elements formed on conductive structures and a cap layer located over the storage elements and the conductive structures. It further includes an interlevel dielectric (ILD) layer over the cap layer, where the ILD layer comprises trenches reaching a top portion of the storage elements, and via openings. The device also has a conductive material formed in the trenches and the via openings, where the conductive material makes contact with the storage elements and forms interlevel vias in the via openings.