Local Data Lines in Memory Arrays for Parasitic Capacitance Reduction
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Solution Overview
Problem
Parasitic capacitance in memory devices slows down data reading due to long data lines that capacitively couple with other conductors, increasing the time required to change voltage and affecting memory device performance.
Innovation Solution
Implementing local data lines that are shorter than conventional data lines, with global data lines connecting multiple local data lines to a sense amplifier, reducing capacitance and impedance, and using a process that maintains the pattern of transistors in the array to facilitate smaller feature formation and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If long data lines are used to service multiple capacitors across a memory block, then the data line can serve more capacitors, but parasitic capacitance increases which slows down the voltage change rate and increases data read time
Solution Approach 1:
The patent divides the memory block into multiple segments, each with its own local data line. Instead of one long data line serving all capacitors, multiple shorter local data lines serve smaller groups of capacitors respectively. This segmentation reduces the capacitance of each data line while maintaining the ability to service multiple capacitors through the hierarchical structure of local and global data lines.
2Area of stationary object
If long data lines are used to extend across an entire memory block, then more capacitors can be accessed, but the data line capacitance increases which increases the time required to read data
Solution Approach 1:
The patent introduces a hierarchical dimension to the data line structure by organizing data lines into multiple levels: local data lines that serve small groups of capacitors, and global data lines that connect these local lines to sense amplifiers. This dimensional organization allows the memory block to be covered extensively through global lines while keeping individual local lines short, thus reducing capacitance and data read time.
3Speed
If shorter local data lines are implemented to reduce parasitic capacitance, then the voltage change rate increases, but the device complexity increases due to additional global data lines and switching mechanisms
Solution Approach 1:
The global data lines serve multiple functions: they connect multiple local data lines to sense amplifiers, act as data transmission paths, and can be selectively activated based on which memory segment is being accessed. This multi-functionality reduces the need for completely separate dedicated lines for each function, thereby managing complexity while maintaining high speed performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the time constant of the path between the sense amplifier and memory cells, enhancing the response speed of the sense amplifier and allowing for smaller storage devices, which can reduce memory array size and cost.
Implementation Method 1
Parasitic capacitance is known to slow the rate at which the capacitor storing data changes the data line voltage, thereby increasing the amount of time it takes to read data from the capacitor.
Data Source
AI summary
Disclosed are methods, systems and devices, including a device having a fin field-effect transistor with a first terminal, a second terminal, and two gates. In some embodiments, the device includes a local data line connected to the first terminal, at least a portion of a capacitor plate connected to the second terminal, and a global data line connected to the local data line by the capacitor plate.