Self-Gated RRAM Cell Vertical Cross Array Crosstalk Suppression
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Solution Overview
Problem
The vertical cross array structure of RRAMs faces misreading and crosstalk issues due to the lack of integration of gated tubes, leading to restricted integration scale and read/write operations, and high production costs in multi-layer stacked structures.
Innovation Solution
A self-gated RRAM cell is developed with a stacked structure of conductive lower electrodes, a vertical trench, a M8XY6 gated layer on the trench's inner wall and bottom, a resistance transition layer on the gated layer, and a conductive upper electrode, eliminating the need for external diodes or transistors by utilizing the non-linear resistance characteristics of the M8XY6 gated layer and resistance transition layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a passive cross array structure is used for RRAM, then the cell area can be minimized to 4F2, but crosstalk effect and misreading occur when adjacent intersection points are in low resistance state
Solution Approach 1:
The patent applies self-service by enabling the RRAM cell to perform gating function through its own non-linear resistance characteristics. The resistance transition layer exhibits voltage-dependent resistance behavior that automatically prevents crosstalk without requiring external gating structures, thus maintaining small cell area while improving reading accuracy
Solution Approach 2:
The patent utilizes parameter changes by exploiting the non-linear resistance characteristics of the resistance transition layer. The resistance state changes based on applied voltage parameters, allowing the cell to differentiate between actual low resistance state and crosstalk-induced low resistance, thereby resolving the misreading problem
2Quantity of substance
If multi-layer stacked structure is used to increase storage density, then storage density per unit area increases, but production cost significantly increases due to repeated photolithograph processes
Solution Approach 1:
The patent applies dimensionality change by transitioning from horizontal multi-layer stacking to vertical cross array structure. This vertical integration approach reduces the number of photolithograph steps required while maintaining high storage density, thereby lowering production costs
Solution Approach 2:
The patent implements multi-functionality by integrating the gated tube structure within the vertical cross array configuration. This unified structure simultaneously achieves gating function, storage function, and reduced process complexity, eliminating the need for separate gating components and simplifying manufacturing
3Ease of manufacture
If vertical cross array structure is used to reduce production cost, then photolithograph steps are reduced, but integration of gated tube becomes very difficult
Solution Approach 1:
The patent applies merging by combining the gated tube structure with the vertical cross array structure into a unified integrated design. The resistance transition layer serves both as part of the vertical array structure and as the gating mechanism, eliminating the need for separate gating components and simplifying integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution prevents misreading and crosstalk in the vertical cross array structure, enabling high-density 3D storage with reduced production costs and a simple, integrated design, as the RRAM unit relies on its own non-linear resistance characteristics for self-gating functionality.
Implementation Method 1
utilizing the non-linear resistance characteristics of the M8XY6 gated layer and resistance transition layer
Data Source
AI summary
The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M8XY6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M8XY6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell. It may not depend on a gated transistor and a diode, but relies on a non-linear variation characteristic of resistance of its own varied with voltage to achieve a self-gated function, which has a simple structure, easy integration, high density and low cost, capable of suppressing a reading crosstalk phenomenon in a cross array structure; and is also adapted for a planar stacked cross array structure and a vertical cross array structure, achieving 3D storage with a high density.