Vertical Semiconductor Device Stacking for Low Aspect Ratio Fabrication
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Solution Overview
Problem
The existing methods for manufacturing vertical semiconductor devices face challenges in forming openings with small widths and high aspect ratios, making it difficult to create stacked layers and pattern filling, especially as the number of layers increases.
Innovation Solution
The proposed solution involves a vertical semiconductor device design with a substrate, semiconductor patterns, gate structures, and insulating interlayer patterns, where the gate structures and interlayer patterns are strategically stacked and etched to reduce the complexity of forming openings, allowing for a reduced height and low aspect ratio, facilitating the formation of word lines and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked layers is increased to improve integration degree, then the integration degree of memory devices is improved, but it becomes increasingly difficult to form openings with small width and high aspect ratio
Solution Approach 1:
The patent transitions from horizontal transistor arrangement to vertical stacking, changing the spatial dimension of device integration. Multiple transistors are stacked in the vertical direction (third direction) rather than arranged horizontally, enabling higher integration density while maintaining manufacturability through controlled formation processes
2Productivity
If the number of stacked layers is increased to improve integration degree, then the integration degree of memory devices is improved, but the aspect ratio of openings becomes increasingly high making pattern filling difficult
Solution Approach 1:
The patent performs preliminary formation of gate structures and insulation layers before creating the final openings. By pre-forming these structures in a controlled manner, the subsequent opening formation process deals with reduced aspect ratios, making pattern filling more manageable despite the increased number of stacked layers
3Ease of manufacture
If the height of the device is reduced to simplify manufacturing, then the ease of manufacture is improved, but the integration degree may be compromised
Solution Approach 1:
The patent maintains high integration degree by utilizing vertical stacking in the third direction. The device height in the vertical direction is optimized to be manageable, while integration density is achieved through the stacked arrangement of transistors and gate structures rather than increasing horizontal footprint
Data Source
AI summary
A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively.