3D Memory Direct Source Contact via Backside Dielectric Extraction
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Solution Overview
Problem
Metal oxide blocking dielectrics in three-dimensional memory devices occupy significant volume, hindering scaling and are difficult to etch anisotropically, which limits the scalability and efficiency of the memory structure.
Innovation Solution
A method for isotropically etching metal oxide blocking dielectrics from the backside in a manner conducive to device scaling, employing discrete source straps for direct source contact to semiconductor channels, and forming a memory stack structure with a metal oxide blocking dielectric that directly contacts each layer within the alternating stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal oxide blocking dielectrics are used in three-dimensional memory devices, then device reliability is improved, but device volume increases and scaling is hindered
Solution Approach 1:
The patent extracts the metal oxide blocking dielectric from the conventional planar position and relocates it to the backside of the memory device, forming a recess structure. This extraction and relocation reduces the overall device volume while maintaining the essential blocking function, thereby resolving the contradiction between reliability improvement and volume reduction for scaling.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional structure by moving the blocking dielectric to the backside and forming vertical recesses. This dimensional change allows the blocking function to be achieved without increasing the planar footprint, enabling continued scaling of the memory device.
2Reliability
If metal oxide blocking dielectrics are used, then device performance is improved, but manufacturing complexity increases due to difficult anisotropic etching
Solution Approach 1:
Instead of attempting difficult anisotropic etching of the metal oxide blocking dielectric in the conventional planar configuration, the patent inverts the approach by forming the blocking dielectric in vertical recesses on the backside. This inversion transforms the manufacturing challenge into a more manageable process using standard etching techniques, thereby improving ease of manufacture while maintaining device performance.
3Ease of manufacture
If conventional planar structures are used, then manufacturing is easier, but device density and scalability are limited
Solution Approach 1:
The patent employs three-dimensional vertical stacking and backside recess structures to increase device density without significantly complicating the manufacturing process. By utilizing the vertical dimension and backside area, the design achieves higher productivity and scalability while maintaining relative manufacturing simplicity through standardized fabrication techniques.
Data Source
AI summary
A strap level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. An array of memory stack structures is formed through the alternating stack and the strap level sacrificial layer. Each memory film in the memory stack structures includes a metal oxide blocking dielectric. After formation of a source cavity by removal of the strap level sacrificial layer, an atomic layer etch process can be employed to remove portions of the metal oxide blocking dielectrics at the level of the source cavity. Outer sidewalls of semiconductor channels in the memory stack structures are exposed by additional etch processes, and a source strap layer is selectively deposited in the source cavity in contact with the semiconductor channel. If the spacer material layers are sacrificial material layers, all volumes of the sacrificial material layers can be replaced with the electrically conductive layers.