Solid-State Devices TRIZ Cases

Stepped surface regions integrate passive driver circuits within three-dimensional memory stacks.

A polar organic solvent buffer layer enables uniform quantum dot deposition via inkjet printing.

Distinct gate electrode heights in a hybrid substrate structure eliminate lithography for region selection, simplifying manufacturing complexity.

Lattice mismatch induces tensile stress in active pillars, boosting NMOS current drivability while maintaining high integration density.

Segmented inorganic barriers prevent water oxygen corrosion of organic light emitting devices.

A light guide portion uses high and low refractive index parts to direct light toward photoelectric conversion areas.

Stacked semiconductor layers stabilize driving transistor characteristics to maintain high aperture ratios and brightness in ultra high resolution displays.

A thin film transistor array substrate uses a curved active layer to expand gate voltage driving range.

A rod lens array focuses visible light from a scintillating layer onto an image sensor.

Pulsed laser ablation and ultrasonic vibration separate epitaxy substrates, resolving transfer rate bottlenecks in micro LED manufacturing.

Oblique cathodic sputtering deposits variable resistance storage elements atop conductive pillars for non-volatile memory circuits.

A metal oxide blocking dielectric relocates to the backside of a three-dimensional memory stack to enable direct source contact with semiconductor channels.

Docking alkali metal complexes to heteroaryl groups alters dipole moments, resolving low glass transition temperatures that limit high-current device lifespan.

A multi-tone photoresist mask with varying thicknesses defines lightly doped regions in poly-Si thin film transistors.

Angled reflectors route light laterally to reduce sensor height, enabling fingerprint imaging through thick cover glass without structural cutouts.

Distinct gate redox-couples tune OECT threshold voltages, resolving the trade-off between device complexity and electrical versatility.

Recessed channels in an umbrella-type absorber increase sheet resistance and absorption while reducing thermal mass for faster response.

Multilayer substrate with embedded bare chips and ground layers shields bus lines, reducing high-frequency noise interference in thin hard disk drives.

Air gaps formed by epitaxial lateral growth in trenches reduce parasitic capacitance and power consumption while maintaining reliable device isolation.

A closed contour encapsulation seals OLED side gaps while electrically contacting the counter electrode.

Gate induced drain leakage current enables channel pre-charge in memory select transistors.

Segmenting the metal oxide into a horizontal electrode plate decouples it from the via volume, reducing resistance and enabling tunable top electrode volume.

A photosensitive resin composition with specific binder resins enables low-temperature curing for pattern formation.

A bump spacer on a common electrode maintains uniform substrate gaps, preventing deformation from external forces that damage substrates.

Sidewall insulating layer electrically isolates metal shield grounds from BARC layers in backside illuminated image sensors.

An ESD protection circuit uses a discharge acceleration mechanism to rapidly route electrostatic current away from sensitive integrated circuit nodes.

An in-cell touch sensor merges with the display structure to eliminate separate films, reducing device thickness and enabling foldability.

Extending target pins across shared cell boundaries increases routing flexibility without expanding the defined area of individual integrated circuit cells.

Fixed-frequency PWM control prevents indeterminate switching noise in adjacent logic circuits while maintaining stable voltage regulation under light loads.

Composite adhesive layers containing inorganic particles bond flexible OLED panels while maintaining structural integrity during folding operations.

A three-molded body semiconductor device uses segmented transparent and light-blocking resin structures to suppress optical crosstalk between channels.

A composite metal-polysilicon gate electrode prevents dishing during polishing in high-voltage MISFET regions, reducing boundary area.

Two-step energizing mitigates phosphorus segregation at nugget edges, resolving cross-tension strength failures in high-strength steel spot welded joints.

Non-parallel adsorption molecules increase light absorption rate per unit volume in semiconductor nanoparticle layers.

A porous substrate layer with lower refractive index enhances light extraction from organic light-emitting devices.

Ruthenium-silicon diodes isolate unselected cells by blocking leakage currents, resolving the trade-off between array density and selectivity.

A mixed light-emitting layer doped with a second hole transporting material enhances hole injection in QLED devices.

A current-driven display uses segmented upper electrode regions separated by spacers to minimize ambient light reflection.

An array substrate integrates a solar cell structure between the substrate and common electrode to generate electric energy for display operation.

Photoluminescent conjugated polymer nanoparticles replace toxic heavy metals with alkaline earth doped oxides to achieve high purity tunable color rendering.

Segmented phosphor encapsulation exposes flip-type CSP LED electrode pads, preventing contamination and ensuring stable electrical connections.

Parallel impurity regions expand the variable resistance range and improve linear control precision compared to single-channel MOS structures.

Buffer layers bridge energy gaps between p-n junctions and emissive units, resolving misalignment issues.

A line-shaped active region structure stabilizes phase-change memory devices by defining source and drain regions between word lines.

Shared charged regions in a common charge-trap layer improve storage density and charge retention without adding separate structural components.

Composite pad layers prevent corrosion-induced resistance loss while maintaining high conductivity through integrated manufacturing steps.

Central silicon and peripheral tungsten in electrode films reduce interconnect resistance while minimizing tungsten usage to prevent wafer warping.