Charge-Trap Memory Shared Regions for Density
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Solution Overview
Problem
Existing non-volatile memory (NVM) devices face challenges in increasing storage density and maintaining charge retention over time due to the traditional one-to-one relationship between control gates and memory cells, leading to charge dissipation and degradation in reliability.
Innovation Solution
The introduction of additional electrically-charged regions in a common charge-trap layer not uniquely associated with any single control gate, allowing for programming and reading by a read/write unit that applies voltages to multiple gates simultaneously, thereby improving data storage density and charge retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional electrically-charged regions are introduced in the common charge-trap layer, then data storage density is improved, but device complexity increases
Solution Approach 1:
The common charge-trap layer serves multiple functions: it stores data under individual control gates and simultaneously accommodates additional shared charged regions that are not uniquely associated with any single gate. This multi-functional use of the charge-trap layer increases storage density without adding separate structural components for each storage region.
Solution Approach 2:
Multiple charged regions (both gate-specific and shared) are merged into a single common charge-trap layer, allowing simultaneous storage functions. The shared charged regions are combined with individual gate-controlled regions in the same physical layer, increasing density while maintaining a unified structure.
2Reliability
If additional electrically-charged regions are created by applying programming voltages to multiple gates simultaneously, then charge retention is improved, but programming complexity increases
Solution Approach 1:
The common charge-trap layer acts as an intermediary that receives charge from multiple control gates simultaneously. When programming voltages are applied to multiple gates, the charge-trap layer mediates the charge distribution, creating shared charged regions that improve retention by distributing charge more evenly across the memory structure.
Solution Approach 2:
The system dynamically adjusts charge distribution by allowing flexible programming of multiple gates simultaneously. The read/write unit can dynamically create charged regions in response to programming operations, adapting the charge distribution pattern to improve retention based on the specific programming scenario.
3Reliability
If the read/write unit creates and manages additional charged regions, then operational reliability is improved, but control complexity increases
Solution Approach 1:
The read/write unit is designed with multi-functionality to both create and read charged regions in the common charge-trap layer. It can apply programming voltages to multiple gates simultaneously to create shared charged regions and also read data by detecting charge states, providing unified control for both programming and reading operations.
Solution Approach 2:
The read/write unit autonomously manages the creation and detection of charged regions without requiring external intervention for each operation. It self-manages the programming voltages applied to multiple gates and the subsequent reading operations, reducing the need for additional control circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances storage density and reliability by creating electrically-charged regions that act as boundaries to prevent charge spreading, maintaining data integrity and stability over time.
Implementation Method 1
multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer
Implementation Method 2
The R/W unit is configured to modify a thermal coefficient of the device by changing an amount of electrical charge in the given region
Data Source
AI summary
A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.