Line-Shaped Active Region for PCRAM Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in manufacturing high-integration phase-change random access memory (PCRAM) devices lies in forming vertical pillars, which are difficult due to increased aspect ratios and process complexities, particularly in improving off-current characteristics and preventing diode leaning phenomena.
Innovation Solution
The semiconductor memory device employs a line-shaped active region structure with source and drain regions formed between word lines, using a method that includes forming sacrificial layers, ion implantation, and depositing storage layers to create a stable structure that reduces the height of the device and enhances transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the height of the vertical pillar is increased to improve off current characteristic, then the off current characteristic is improved, but the aspect ratio is increased causing process difficulty and diode leaning
Solution Approach 1:
The patent transitions from a vertical pillar structure to a planar structure with source and drain regions formed between word lines. This dimensional change eliminates the need for high aspect ratio vertical pillars while achieving the required off current characteristics through the planar device geometry and material composition.
Solution Approach 2:
Instead of increasing vertical height to improve off current characteristics, the patent inverts the approach by optimizing the planar dimensions and material properties. The off current is improved through the planar structure's inherent characteristics rather than vertical scaling, thereby avoiding aspect ratio issues.
2Length of moving object
If the height of the vertical pillar is increased to ensure effective channel length, then the effective channel length is ensured, but the aspect ratio is increased causing process difficulty and leaning phenomenon
Solution Approach 1:
The patent replaces the vertical pillar structure with a planar structure where the effective channel length is defined by the horizontal distance between source and drain regions. This allows sufficient channel length to be achieved without increasing vertical height, thereby maintaining low aspect ratio and simplifying the manufacturing process.
3Productivity
If a vertical pillar structure is used to increase integration degree, then the integration degree is increased, but the minimum feature size reduction is limited due to resolution limitation
Solution Approach 1:
The patent adopts a planar structure that allows for finer feature size control in the lateral dimensions, which are less constrained by vertical resolution limitations. This enables continued scaling and integration density improvement without being bottlenecked by the difficulty of forming high aspect ratio vertical pillars at small feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved integration density and reduced chip size in PCRAM devices by stabilizing the structure and increasing the effective channel length, thereby simplifying the manufacturing process and preventing diode leaning.
Implementation Method 1
The phase-change material is changed into an amorphous state or a crystalline state depending on the temperature to define RESET (or logic '1') or SET (or logic '0')
Implementation Method 2
performing ion implantation of impurities on the active region at both sides of each of the word lines to form source regions in the implanted active region corresponding to the posts and drain regions in remaining implanted active region
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.