3D Memory Passive Devices Stepped Surface Integration
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Solution Overview
Problem
Current semiconductor technologies face challenges in integrating passive devices, such as capacitors and resistors, seamlessly with three-dimensional memory devices, particularly in forming structures that allow for efficient electrical connectivity and compatibility within complex stacked architectures.
Innovation Solution
The development of a three-dimensional memory device structure that includes a memory device region with non-volatile memory devices, a peripheral device region with active driver circuits, and a stepped surface region containing passive driver circuits, utilizing a stack of alternating electrically insulating and conductive layers over a substrate, with dielectric material and contact via structures to facilitate electrical connections and stepped surfaces for capacitor formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive devices are integrated with three-dimensional memory devices using conventional planar structures, then manufacturing simplicity is maintained, but electrical connectivity and compatibility within stacked architectures are insufficient
Solution Approach 1:
The patent transitions from conventional planar structures to three-dimensional stacked architectures by forming alternating conductive and insulating layers vertically. Passive devices such as capacitors are integrated within this vertical stack, enabling efficient electrical connectivity in the third dimension while maintaining compatibility with 3D memory device architectures.
Solution Approach 2:
The patent embeds passive devices within the stacked structure of memory devices. Capacitors are formed by utilizing conductive layers and dielectric materials that are already present in the vertical stack, nesting multiple functional components (memory cells and passive devices) within a single integrated structure to improve connectivity without proportionally increasing overall device complexity.
2Reliability
If alternating conductive and insulating layers are formed to create stepped surfaces for capacitor formation, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the complete stack of alternating conductive and insulating layers using sequential deposition processes before any patterning or capacitor formation steps. This preliminary formation of the layered structure establishes precise alignment and interfaces early in the manufacturing process, facilitating subsequent capacitor formation while maintaining manufacturing feasibility.
3Ease of manufacture
If passive devices are formed in a separate peripheral device region, then integration complexity is reduced, but electrical connectivity and compatibility with memory device region are limited
Solution Approach 1:
The patent merges the formation of passive devices with the memory device fabrication process by using the same alternating conductive and insulating layer stack for both memory cell formation and passive device formation. This unified approach eliminates the need for separate peripheral device regions while maintaining manufacturing simplicity, as both device types share common structural elements and processing steps.
Data Source
AI summary
A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.