CMOSFET Isolation Using Epitaxial Lateral Growth Air Gaps
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Solution Overview
Problem
Existing CMOSFET devices face challenges in achieving effective electrical isolation due to high integration density, leading to issues like current leakage, power consumption, and functional degradation, with prior isolation methods being insufficient in reducing silicon area usage.
Innovation Solution
A method involving a silicon-on-insulator (SOI) substrate with buried dielectric layers and epitaxial lateral growth layers that form air gap regions overlying buried dielectric layers, creating trenches and sidewall spacers to minimize capacitance and enhance isolation without additional processing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional isolation methods are used in high integration density CMOSFET devices, then device isolation is achieved, but silicon area is excessively consumed and capacitance is high
Solution Approach 1:
The patent introduces air gap regions in the vertical dimension above the buried dielectric layer to provide electrical isolation. By utilizing the vertical space above the substrate rather than expanding lateral isolation trenches, the invention achieves effective electrical isolation while minimizing lateral silicon area consumption. The air gap acts as a dielectric medium that electrically isolates devices without requiring extensive lateral spacing.
Solution Approach 2:
The patent employs air gap regions as a porous/void structure to achieve electrical isolation. The air gaps, formed by removing sacrificial oxide layers, create isolated regions that prevent electrical interference between devices. This porous approach using air as the isolating medium is more area-efficient than solid dielectric materials while maintaining effective electrical isolation.
2Loss of energy
If conventional isolation methods are used in high integration density CMOSFET devices, then device isolation is achieved, but capacitance between devices is high leading to power consumption
Solution Approach 1:
By moving the isolation mechanism to the vertical dimension with air gaps above the buried dielectric layer, the patent reduces lateral capacitance between devices. The air gaps create electrical isolation that minimizes parasitic capacitance without requiring large lateral separation, thereby reducing power consumption associated with charging and discharging device capacitance.
Solution Approach 2:
The patent changes the dielectric parameter by introducing air gaps (low dielectric constant) in the isolation regions. This parameter change reduces the capacitance between adjacent devices compared to using high-k dielectric materials, thereby reducing power consumption while maintaining effective electrical isolation.
3Reliability
If isolation structures are added to ensure electrical isolation, then electrical interference is prevented, but device complexity and processing steps increase
Solution Approach 1:
The patent merges the formation of air gap isolation regions with the existing CMOS fabrication process sequence. The sacrificial oxide layers are formed and removed as part of the standard gate and source/drain processing, integrating the isolation structure creation into the main fabrication flow without adding separate dedicated processing modules.
Solution Approach 2:
The patent performs preliminary formation of sacrificial oxide layers that will later become the air gap isolation regions. These oxide layers are formed early in the process sequence during gate oxidation, before the actual isolation structure is needed, allowing the isolation regions to be created as a byproduct of subsequent processing steps rather than requiring separate addition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach provides excellent electrical isolation with reduced capacitance and power consumption, maintaining device functionality while minimizing silicon area usage and processing complexity.
Implementation Method 1
forming, in the trenches, an epitaxial lateral growth layer. The epitaxial lateral growth layer grows laterally from the opposing sidewalls of the trenches to enclose a portion of the trenches extending into the upper semiconductor layer
Data Source
AI summary
A semiconductor device structure having an isolation region and method of manufacturing the same are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate. A plurality of gates is formed on the SOI substrate. The semiconductor device structure further includes trenches having sidewalls, formed between each of the plurality of gates. The semiconductor device structure further includes an epitaxial lateral growth layer formed in the trenches. The epitaxial lateral growth layer is grown laterally from the opposing sidewalls of the trenches, so that the epitaxial lateral growth layer encloses a portion of the trenches extended into the SOI substrate. The epitaxial lateral growth layer is formed in such way that it includes an air gap region overlying a buried dielectric layer of the SOI substrate.