Split-Gate Memory Gate Electrode Dishing Prevention
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Solution Overview
Problem
Semiconductor devices with metal gate electrodes in high-voltage and low-voltage MISFET regions face challenges such as long gate lengths in high-voltage MISFETs leading to dishing issues and increased boundary region area, while preventing dishing in polysilicon gate electrodes results in increased boundary region area, affecting performance.
Innovation Solution
A method involving forming a control gate and memory gate electrodes in the memory cell region, using a metal-nitride-containing metal film in high-voltage MISFET regions and a conductive silicon film, and patterning to form specific gate electrodes, with a low-dielectric constant film in low-voltage MISFET regions to optimize gate lengths and reduce boundary region area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a metal gate electrode is formed by filling a trench with a conductive film and polishing it in the high-voltage MISFET region, then the gate electrode can be formed, but dishing occurs during polishing
Solution Approach 1:
The patent changes the material parameter from conventional conductive film to a composite structure of metal film (such as tungsten) and polysilicon film. This material substitution prevents dishing during polishing while maintaining the required electrical characteristics for high-voltage MISFET operation.
Solution Approach 2:
The gate electrode uses a composite structure combining metal film and polysilicon film. The metal film provides low resistance and the polysilicon film provides mechanical strength and planarity, preventing dishing during CMP polishing while maintaining electrical performance.
2Shape
If a gate electrode made of a polysilicon film is formed in the high-voltage MISFET region to prevent dishing, then dishing is prevented, but the proportion of boundary region area increases
Solution Approach 1:
The patent changes the material composition to a composite of metal film and polysilicon film, allowing the gate electrode to maintain planarity (prevent dishing) while reducing the boundary region area compared to using polysilicon alone. The metal component enables better adhesion and reduced transition zone requirements.
3Reliability
If a long gate length is used in the high-voltage MISFET, then the device can handle high voltage, but dishing occurs during polishing
Solution Approach 1:
The gate electrode employs a composite structure of metal film and polysilicon film. The metal film (e.g., tungsten) provides the necessary electrical properties for high-voltage operation while the polysilicon component ensures planarity during polishing, preventing dishing even in long gate length structures.
Solution Approach 2:
The patent modifies the material parameters of the gate electrode by substituting conventional conductive materials with a metal-polysilicon composite. This change maintains the electrical performance required for high-voltage capability while eliminating the dishing defect during polishing processes.
Data Source
AI summary
To provide a semiconductor device having improved performance. A method of manufacturing the semiconductor device includes forming, after formation of a control gate electrode and a memory gate electrode, a conductive film on an insulating film made of a high-dielectric-constant film via a metal film; patterning the conductive film and thereby forming a gate electrode including the metal film and the conductive film in a high-voltage MISFET region, while forming a metal film portion and a conductive film portion in a low-voltage MISFET region; and then, removing the conductive film portion from the low-voltage MISFET region, forming another conductive film on the metal film portion, and forming a gate electrode including the metal film portion and the another conductive film.