Ultra High Resolution LCD Compensation Thin Film Transistor
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Solution Overview
Problem
Ultra high resolution liquid crystal displays face challenges in maintaining high aperture ratios and maximum brightness due to the increased size of thin film transistors relative to pixel areas, particularly at resolutions over 500PPI, which reduces the effective aperture ratio and brightness.
Innovation Solution
Incorporating a compensation thin film transistor with a polycrystalline semiconductor material at each pixel area to compensate for the Off-current feature of the driving thin film transistor, while optimizing the structure to minimize the non-aperture area ratio, such as by overlapping semiconductor layers with the gate line and using a 'V' or slanted segment shape to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a compensation thin film transistor is added to each pixel area, then the Off-current feature is compensated and transistor characteristics are stabilized, but the non-aperture area ratio increases and aperture ratio decreases
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration by placing the compensation TFT vertically over the driving TFT. The semiconductor layers are stacked at different heights with gate lines extending in the planar direction, utilizing vertical space to accommodate the compensation transistor without increasing the pixel footprint, thereby maintaining aperture ratio while achieving compensation functionality.
Solution Approach 2:
The compensation TFT is nested within the same pixel area as the driving TFT by stacking the semiconductor layers vertically. The first semiconductor layer and second semiconductor layer are positioned at different heights, with the compensation TFT structure embedded within the vertical space of the pixel region, allowing both transistors to coexist in a compact configuration that minimizes non-aperture area.
2Measurement precision
If the pixel area is reduced for ultra high resolution over 500PPI, then the resolution is improved, but the aperture ratio and maximum brightness are degraded
Solution Approach 1:
The patent utilizes vertical stacking to reduce the planar footprint of the transistor structures. By arranging semiconductor layers and gate lines in three-dimensional space rather than purely planar configurations, the pixel area is minimized, enabling ultra high resolution displays while preserving sufficient aperture area for high brightness performance.
Solution Approach 2:
The patent segments the transistor structure into multiple stacked layers with gate lines extending in the planar direction and semiconductor layers positioned at different heights. This segmentation allows efficient space utilization within the pixel area, reducing the non-aperture area ratio and maintaining high aperture ratio despite the reduced pixel size required for 500PPI or higher resolutions.
3Measurement precision
If the pixel area is reduced for ultra high resolution over 500PPI, then the resolution is improved, but the non-aperture area ratio increases
Solution Approach 1:
The patent employs vertical stacking of semiconductor layers and gate lines to reduce the planar area occupied by transistor structures. By utilizing the third dimension (height) to accommodate compensation TFT components, the non-aperture area ratio is minimized, allowing ultra high resolution displays with maintained aperture ratios.
Solution Approach 2:
The patent merges the driving TFT and compensation TFT into a compact stacked configuration within the same pixel area. The gate lines are extended in the planar direction to serve both transistors, and semiconductor layers are stacked vertically, combining multiple functions into a space-efficient structure that reduces the non-aperture area ratio for ultra high resolution displays.
Data Source
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AI summary
The present disclosure relates to an ultra high resolution liquid crystal display having a compensation thin film transistor. The present disclosure provides an ultra high density liquid crystal display comprising: a gate line on a substrate; a first gate insulating layer on the gate line; a first semiconductor layer crossing the gate line on the first gate insulating layer; a second gate insulating layer on the first semiconductor layer; a second semiconductor layer crossing the gate line on the second gate insulating layer; an intermediate insulating layer on the second semiconductor layer; a data line connected to the first semiconductor layer on the intermediate insulating layer; and a drain electrode connected to the second semiconductor layer on the intermediate insulating layer.