Fin Gate Semiconductor Device With Lattice Constant Mismatch
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Solution Overview
Problem
Current semiconductor devices face limitations in integration density and high operation current requirements for next-generation memory devices, particularly in 3D transistor structures with vertical or fin gate configurations, which hinder the development of high-capacity, high-speed, and low-power memory solutions.
Innovation Solution
A semiconductor device with an active pillar having a first semiconductor layer with a larger lattice constant for the channel region and a surrounding second semiconductor layer with a smaller lattice constant, creating tensile stress and improving electron mobility, is combined with a fin gate structure that overlaps the active pillar's surfaces, enhancing current drivability and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a 3D transistor structure with fin gate is used to improve integration density, then integration density increases, but high operation current is required to maintain high resistance variable characteristics
Solution Approach 1:
The patent applies local quality by creating different stress conditions in different regions of the active pillar. The inner region is subjected to tensile stress while the outer region experiences compressive stress, optimizing carrier mobility locally in each region to reduce operation current while maintaining high integration density
Solution Approach 2:
The patent changes physical parameters by introducing stress through lattice constant differences between inner and outer semiconductor layers. This parameter change modifies the electrical characteristics of the transistor channel, enabling lower operation current for the same integration density
2Reliability
If lattice constant difference is optimized to increase electron mobility, then electron mobility and current drivability improve, but manufacturing complexity increases
Solution Approach 1:
The patent uses composite materials by combining different semiconductor layers with different lattice constants (e.g., SiGe and Si) to create the active pillar structure. This composite approach achieves the desired stress distribution and electron mobility improvement while using commercially available semiconductor materials and standard epitaxial growth processes
Solution Approach 2:
The patent controls the lattice constant parameter by adjusting the Ge concentration in SiGe layers during epitaxial growth. By precisely controlling this parameter within standard manufacturing tolerances, the desired tensile and compressive stress conditions are achieved without requiring complex manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases electron mobility and current drivability of NMOS transistors, improving the operational characteristics and integration density of 3D transistors, thereby addressing the limitations of existing memory devices by optimizing the lattice constant difference and fin gate configuration.
Implementation Method 1
the inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant
Implementation Method 2
a difference between a lattice constant of the first semiconductor layer and a lattice constant of the second semiconductor layer causes tensile stress in a region where the first semiconductor layer and the second semiconductor layer are interfaced
Data Source
AI summary
A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. The inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant.