Curved Active Layer Thin Film Transistor for OLED Gray Scale Control
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Solution Overview
Problem
Existing organic light-emitting display apparatuses face challenges in achieving high resolution and display quality due to limitations in the design of thin film transistor arrays, particularly in the configuration of active layers and capacitors, which affect the control of gray scale values and the accuracy of light emission.
Innovation Solution
A thin film transistor array substrate is designed with a curved active layer for the driving thin film transistor, a capacitor structure with overlapping electrodes, and a mesh structure for the driving voltage line, along with compensation and emission control transistors, to enhance the control of driving current and improve display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional flat active layer is used in the driving thin film transistor, then the device structure is simple, but the driving range of gate voltage is limited and gray scale control accuracy is insufficient
Solution Approach 1:
The active layer is designed with a curved configuration instead of a conventional flat structure. This curvature increases the effective area of the active layer within the same device footprint, thereby expanding the driving range of gate voltage and improving gray scale control accuracy without proportionally increasing device complexity
Solution Approach 2:
The patent transitions from a two-dimensional flat active layer to a three-dimensional curved active layer structure. This dimensional change allows for increased effective area and improved voltage control range while maintaining a compact device layout
2Reliability
If the capacitor electrode area is increased to improve holding capacity, then the capacitor can maintain voltage more effectively, but the pixel area increases reducing resolution
Solution Approach 1:
The capacitor structure is designed with nested overlapping electrodes where the first electrode and second electrode are positioned in a stacked configuration. This nesting approach maximizes the effective capacitor area within a compact footprint, improving voltage holding capacity without proportionally increasing pixel area
Solution Approach 2:
The capacitor transitions from a planar side-by-side electrode layout to a three-dimensional overlapping stacked structure. This vertical arrangement increases the effective capacitor area without expanding the horizontal pixel footprint, thereby maintaining high resolution
3Power
If the driving voltage line is made thicker to reduce resistance, then current transmission is improved, but the line occupies more space and complicates the mesh structure
Solution Approach 1:
The driving voltage line is divided into multiple segments forming a mesh structure. This segmentation allows each segment to be optimized for current transmission while the distributed mesh layout reduces overall resistance without requiring any single line to be excessively thick
Solution Approach 2:
The driving voltage line transitions from a simple linear configuration to a two-dimensional mesh structure. This dimensional expansion distributes current pathways across multiple routes, reducing resistance and improving transmission efficiency while maintaining space efficiency
Data Source
AI summary
A substrate includes a driving transistor, a capacitor, a driving voltage line, and a connection line. The driving transistor has a gate electrode overlapping a channel region of a curved active layer. The capacitor has a first electrode is formed of the gate electrode of the driving transistor and a second electrode overlapping the first electrode. The driving voltage line includes driving voltage line portions on the capacitor and connected to edges of the second electrode of the capacitor. The first connection line is located at a portion of a region on the capacitor separated from the driving voltage line. A via hole is on the first connection line.