3D Memory Device Divided Drain Select Gate Lines
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling and cost as feature sizes approach a limit, necessitating a more efficient memory density solution.
Innovation Solution
A 3D memory device architecture with a doped semiconductor layer, stack structure, and channel structure, where the select gate line is insulated from adjacent structures, allowing for increased memory density by forming vertically oriented memory cell transistors and reducing the width of the semiconductor structure compared to the channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell scaling is continued, then memory density increases, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) vertically-oriented memory strings. Memory cells are arranged in vertical stacks extending through multiple layers, allowing density scaling without increasing lateral footprint or manufacturing complexity. This dimensional change enables continued density improvement while avoiding the complexity penalties of further planar scaling.
2Device complexity
If select gate lines are shared between adjacent memory cells, then device complexity is reduced, but electrical interference between adjacent cells increases
Solution Approach 1:
The patent divides the select gate line into separate, isolated segments that wrap around individual memory strings. Each select gate line is electrically isolated from adjacent strings by insulating layers, preventing electrical interference while maintaining structural organization. This segmentation allows shared gate lines to serve multiple strings without causing harmful coupling effects.
Solution Approach 2:
The patent introduces insulating layers as intermediary materials between adjacent select gate lines and memory strings. These insulating layers act as electrical barriers that prevent harmful interference while allowing the select gate lines to function. The insulating intermediary enables close proximity positioning of gate lines to multiple strings without direct electrical coupling.
3Quantity of substance
If semiconductor structure width is reduced to increase density, then memory density increases, but insulation efficiency between adjacent cells decreases
Solution Approach 1:
The patent moves insulation from a lateral dimension to a vertical dimension by implementing multi-layer insulating structures that wrap around memory strings in the vertical direction. This vertical insulation approach maintains effective electrical isolation even as lateral dimensions are reduced for higher density. The insulating layers are positioned at multiple vertical levels to ensure complete isolation.
Solution Approach 2:
The patent implements nested insulating structures where insulating layers are positioned concentrically around memory strings and channel structures. Multiple insulating layers are nested at different radial and vertical positions, creating comprehensive electrical isolation. This nested arrangement maintains insulation efficiency while allowing reduced spacing between adjacent memory strings for increased density.
Data Source
AI summary
A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, a channel structure, and a semiconductor structure. The stack structure includes a plurality of word lines and a select gate line formed on the doped semiconductor layer. The channel structure extends through the plurality of word lines along a first direction and in contact with the doped semiconductor layer. The semiconductor structure extends through the select gate line along the first direction and in contact with the channel structure. The select gate line extends along a second direction perpendicular to the first direction, and the drain select gate line around the semiconductor structure is insulated from the drain select gate line around an adjacent semiconductor structure. A width of the semiconductor structure is less than a width of the channel structure.