Solid-State Devices TRIZ Cases

A groove-spanning electrode layout cuts light-shielding area between opposite-polarity electrodes, improving display panel opening rate.

Direct bonding of monochromatic optical elements enables fine pixel pitch and bright AR displays while avoiding adhesive loss and color-stack complexity.

Horizontal extension of the light emitting layer avoids conductive-layer edge contact, reducing surface recombination and improving carrier injection.

A layered transmission area lets optical devices sit under the screen while limiting diffraction, preserving flatness, and maintaining sealing.

A discontinuous cell contact plug in stacked 3D memory boosts integration without finer planar patterning, while supporting electrical reliability.

By mixing converted and direct emitter spectra, this LED structure raises CRI while cutting phosphor content, cost, and light extraction loss.

A non-display light-blocking part suppresses light leakage and seam visibility, improving immersion in tiled display panels.

Alternating tilted micro-LEDs and varied electrode pad spacing correct viewing-angle color shift and reduce parasitic capacitance ghosting.

Different-width insulating-layer openings cut photomask steps, reduce semiconductor damage, and support smaller high-resolution pixels.

An overlapping conductive and anti-reflection pattern in the upper film layer discharges static and cuts external light reflection for clearer, more reliable displays.

A conductive isolation feature with a dielectric layer eases deep isolation in small pixels while improving light collection and quantum efficiency.

A three-layer oxide and low-band-gap stack absorbs plasma UV photons to protect photodiodes and preserve dark current and quantum efficiency.

Ion implantation, annealing, and germanium condensation create tensile and compressive SOI regions to optimize pFETs and nFETs.

Light-transmitting holes and layered transparent regions raise backplane transmittance while supporting large spliced display panels.

A flat photoresist pattern cuts metal-trace reflectivity while improving Micro LED electrode bonding yield and avoiding parasitic capacitance.

Protective insulating and film layers shield glass-edge side wirings from impact, reducing disconnection and improving display module coupling stability.

A transparent conductive oxide electrode forms a eutectic bond with micro or mini LED electrodes to improve adhesion and cut adhesive cost.

Insulated common electrode lines on a separate layer raise pixel aperture in dual-gate array substrates while keeping data-line count and cost low.

Chamfered reflective electrode borders increase spacing at line overlaps, improving development flow and preventing LCD array short-circuits.

Scattering particles on the insulation film redirect light away from reflective losses, boosting top emission in inorganic LEDs.

Angularly offset word lines across stacked memory tiers cut coupling effects, improving word line speed in compact memory arrays.

Two pixel groups balance high quantum efficiency and saturation resistance, helping detect low-irradiance targets under strong background light.

A cushion-layer adhesive sheet protects wafer protrusions during back grinding by placing them inside an opening that distributes load.

A floating connection line links crack sensing patterns across the active area while staying insulated from sensing electrodes to improve panel reliability.

Separated pads and a current spreading layer enable accurate electrical and optical measurement of micro-sized light-emitting elements.

Overlapping electrode and source line portions compensate bypass gate line capacitance differences to prevent waveform and luminance non-uniformity.

A TFT electrode layout moves electrode ends beyond the gate area to cut short-circuit risk and keep parasitic capacitance consistent.

A lateral reflective film redirects side-emitted light to both end surfaces, boosting display emission efficiency with targeted optical structuring.

Multiple polarizer layers adjust sensor light sensitivity to prevent signal saturation near strong light sources while preserving normal sensing.

Dual porous LED layers with vertical and random pores hold quantum dots to improve light conversion and light extraction in flexible displays.

Position-dependent nanostructures guide light more evenly into each pixel to improve edge sensitivity without lowering resolution.

Separated trench gate groups and an emitter-connected base path help discharge holes during turn-off, cutting loss in macro thinning structures.

Stepped bonding regions and preformed through-stack vias help stacked 3D memory dies improve vertical interconnection reliability.

A side-wrapping encapsulation film seals the substrate-encapsulation junction to block water vapor and reduce Mini LED corrosion risk.

Asymmetric halo implants tied to the source improve SOI transistor linearity and gain without added noise or process complexity.

A raised deep trench isolation surface redirects photons back into photosensitive areas, improving SiPM detection efficiency while limiting crosstalk.

Extension and dummy lines balance coupling capacitance and external noise across sensor panel wires to preserve position detection accuracy.

A buried electrode LED die keeps both contacts accessible from one side while reducing light blockage and simplifying wirebonding.

Dedicated n-well ECO base cells enable post-placement logic changes, flexible routing, and multi-voltage support without extra IC layout iterations.

Vertical overlap of the transistor and light emitting element improves display resolution, reliability, and light extraction with a reflective electrode.

Through-substrate DTI enables a shared floating node in image sensors, preserving photodetector isolation while improving layout efficiency and conversion gain.

A mixed penetrating and non-penetrating light shield layout cuts optical noise in global shutter pixels while preserving sensitivity and charge transfer.

Stepped terrace references guide stacked die placement to prevent cumulative vertical errors while supporting faster, lower-cost chip package assembly.

Reverse-taper wiring and a clad-protected layout improve LED self-assembly accuracy while limiting corrosion and connection defects.

By forming replacement gates before memory cells, higher-temperature processing can create interdigitated electrodes without cell damage.

Optimized subpixel spacing at module interfaces reduces optical loss and angle-dependent color shift in modular light-emitting displays.

Triangular protection layers on stretchable display pixels shield LEDs during stretching while improving light extraction, luminance, and transfer alignment.

Conductive blocks and top wires avoid 30-50 micron height-climbing metal lines, improving micro-LED panel connection reliability.

A multi-touch tablet interface replaces knobs and keyboards in portable ultrasound, improving cleanability, sterility, and ease of use.

Severable or weldable superconducting bridges let qubit inductance be trimmed after fabrication to avoid frequency collisions without harming coherence.

A photoresistor locally heats and melts the binding layer so abnormal Micro LED chips can be removed and replaced without damaging the bond site.

A light-transmitting substrate and non-overlapping metal wiring shrink CMOS sensor packaging while improving light entry and yield.

A thin junction around the photodiode blocks trench-surface carriers, reducing dark current and white pixel defects in CMOS image sensors.

A graded refractive-index layer around nanorod micro-LED sidewalls reduces total internal reflection and boosts display brightness with lower power.

Nano-scale active elements maintain strain at high indium content, reducing defects and improving red LED emission efficiency.

A protruded first electrode layer under a second layer suppresses parasitic resistance and crystal defects, cutting image noise.

Rounded lens corners above 90° reduce stress concentration at the four corners, helping imaging modules prevent lens peeling and improve attachment reliability.

By merging short pillar patterns into longer conductive pillars, this case opens transverse routing space while cutting wiring length and heat.

A thinner outer light-transmissive member conceals the module edge while the covering member still holds the LED array securely.

Curved recess bottoms and doped dielectric sidewalls confine lattice-mismatch dislocations below active pixels, improving image sensor reliability.

Air interstices and low-index encapsulation blocks help closely spaced LEDs reduce photon trapping and improve light extraction.

Near-vacuum bonding prevents temporary base sagging and uneven pressure, improving LED-to-pad bonding yield during display panel assembly.

Curved pixel filters and low-index inter-pixel shielding redirect light to cut color mixing while preserving quantum efficiency in CMOS sensors.

A surge trigger layer under the metal film confines surge current, reducing current concentration and improving heat dissipation.

Overlapping sensitive and insensitive detector regions cuts CT detector dead area, avoids dummy scintillators, and lowers module cost.

Removable curved LED modules with local heat sinks and magnetic mounting create a smoother spherical display with uniform curvature.

A low-index layer between the photoelectric conversion section and electrode blocks evanescent light absorption to preserve quantum efficiency.

Two infrared filters split near-IR into separate bands, enabling higher-level imaging for distance measurement and biological monitoring.

Cantilever supports enable gate-all-around formation on stacked channel layers, increasing 3D transistor density while preserving source-drain access.

A superlattice-buffered RFSOI structure boosts carrier mobility while limiting diffusion and preserving oxide interface quality.

A dichroic prism and UV shielding combine ultraviolet and visible LED output into one beam while reducing LED degradation in biochemical analyzers.

Preformed insulating films and pixel electrodes align rod-type light emitters to improve emission efficiency, cut power use, and avoid shorts.

Shared temperature control and coaxial LED multiplexing stabilize wide-band light intensity for accurate two-wavelength absorption analysis.

A layered touch pixel uses a reference capacitor and dielectric shielding to cut parasitic capacitance and noise for high-resolution sensing.

Segmented sacrificial layers between DRAM bit lines cut etching residue in deep contact holes while preserving capacitor contact size and yield.

Rod-type openings in an insulating layer guide sprayed micro LEDs between electrodes to improve alignment, emission uniformity, and light extraction.

Voltage staging raises unselected NAND cell channel potential to block erase disturb and GIDL on shared bit lines while keeping current low.

A light-absorbing layer and reflective wall suppress LED pixel crosstalk, improving display contrast, luminous efficiency, and color purity.

Different refractive indices between imaging and phase pixels improve autofocus accuracy while keeping pixel structure simpler to manufacture.

Metal structures in the passivation stack block nanowell crosstalk before light enters adjacent guides, cutting noise in dense image sensors.

A donor-acceptor blue TADF material lowers singlet-triplet splitting to speed RISC and raise OLED luminous efficiency.

Close-spaced feeding lines and phase shifter electrodes use insulation and active driving to limit coupling, shorts, and signal distortion.

Threshold compensation and reset control stabilize photoelectric detection current despite driving transistor voltage variation.

Top-layer vias open buried channels across stacked layers, enabling concurrent buried line formation with fewer process steps, less time, and lower cost.

A side-extending fixing structure with turning portions relieves transfer stress and preserves electrode alignment for faster, higher-yield display bonding.

Oblique groove sidewalls enable precise film thickness control in a solid-state imager, improving reliability while avoiding SOI substrate cost.

Non-through recess regions balance plating across dense and sparse wiring areas, preventing height variation and easing stacked-chip packaging.

Edge opening patterns in a polysilicon gate raise threshold voltage and suppress kink effects and GIDL in scaled MV/HV transistors.

Electrochemical porosification and mesa regrowth enable aligned RGB micro-LED emission while reducing InGaN strain and transfer steps.

A second color filter in the contact hole preserves electrical coupling while limiting color tinge and protecting pixel aperture in high-definition LCDs.

Shared first electrodes let red, green, and blue epitaxial wafers transfer together, cutting Micro LED transfer steps, time, and complexity.

Bias voltage is switched by illuminance so the photoelectric converter preserves sensitivity and dynamic range while cutting imaging power use.

A controlled gradient angle at substrate step regions prevents functional layer breakage while keeping display panels thin and high resolution.

A glass pane supports epitaxial semiconductor transfer and contact formation to build sub-1 mm optoelectronic components with precise positioning.

A non-uniform TFT active layer widens non-channel regions to cut resistance and parasitic capacitance, improving LCD image quality.

A plasmonic enhancement layer boosts the Purcell effect in phosphorescent OLEDs, cutting excited-state lifetime and slowing device aging.