Stepped Terrace Die Stacking for Precise Vertical Alignment
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Solution Overview
Problem
Existing assembly techniques for stacked semiconductor chip packages are time-consuming and have low yields due to cumulative vertical position errors, leading to increased costs and limited performance.
Innovation Solution
The use of an assembly component with a pair of stepped terraces that mirror the stepped terrace of the chip package, providing vertical position references for an assembly tool to accurately position semiconductor dies in a stack, thereby reducing mechanical errors and tolerating variations in component sizes and positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing assembly techniques are used to assemble stacked semiconductor chips, then the chips can be connected vertically, but the total vertical position error becomes prohibitively large due to cumulative errors from each chip
Solution Approach 1:
A positioning structure with stepped terraces is introduced as an intermediary component between the assembly tool and the semiconductor chips. This positioning structure provides reference surfaces that enable precise vertical positioning of each chip in the stack, preventing cumulative position errors without requiring excessively tight tolerances on individual chip dimensions.
Solution Approach 2:
The invention changes the reference parameter for vertical positioning from individual chip thicknesses to the stepped terrace heights of the positioning structure. By using the positioning structure's stepped terraces as the primary reference, the system can accommodate variations in chip thickness while maintaining precise overall stack positioning, thus reducing total vertical position error.
2Manufacturing precision
If tight manufacturing tolerances are applied to reduce individual vertical position errors, then the total vertical position error decreases, but the cost of semiconductor dies increases
Solution Approach 1:
The positioning structure serves as a mediator that absorbs dimensional variations. Instead of requiring tight tolerances on expensive semiconductor dies, the positioning structure's stepped terraces provide the precise reference surfaces needed for accurate stacking, allowing standard-tolerance chips to be assembled with high precision.
Solution Approach 2:
The positioning structure segments the positioning function from the semiconductor chips themselves. By separating the positioning reference surfaces (stepped terraces) from the functional chips, the invention allows chips to be manufactured with standard tolerances while still achieving precise stack positioning through the dedicated positioning structure.
3Productivity
If the number of semiconductor chips in a stack is increased to improve performance, then higher density logic and memory can be combined, but the total vertical position error becomes prohibitively large
Solution Approach 1:
The positioning structure with stepped terraces acts as a cumulative error-compensating intermediary for multi-chip stacks. Each chip is positioned relative to the positioning structure's terraces rather than to previous chips, preventing error accumulation even as the number of chips in the stack increases to high densities.
Data Source
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AI summary
An assembly component (100) and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies (310-1 - 310-N) that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace (112-1) at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component (100). In particular, the assembly component may include a pair of stepped terraces (112-1,112-2) that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.