Ferroelectric Memory Interface Layers for Oxygen Defect Control
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Solution Overview
Problem
Ferroelectric field effect transistors (FETs) face device degradation due to oxygen defect generation at the interface between the oxide semiconductor channel and the ferroelectric layer, leading to polarization decay and poor endurance, caused by oxygen migration and intermixing.
Innovation Solution
Incorporating a first insertion layer between the gate electrode and the ferroelectric layer, and a second insertion layer between the ferroelectric layer and the channel layer, both formed using atomic layer deposition, to reduce lattice mismatch, enhance crystalline quality, and prevent oxygen vacancy formation, thereby stabilizing the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a ferroelectric layer is directly contacted with an oxide semiconductor channel layer, then device structure is simple, but oxygen defects are generated at the interface due to oxygen migration and intermixing
Solution Approach 1:
An insertion layer is introduced between the ferroelectric layer and the oxide semiconductor channel layer to act as an intermediary barrier. This insertion layer prevents direct contact between the two materials, thereby blocking oxygen migration and intermixing that would otherwise create oxygen defects at the interface. The insertion layer serves as a protective mediator that maintains the integrity of both adjacent layers while eliminating the harmful oxygen defect generation pathway.
2Reliability
If symmetrical insertion layers are used between gate electrode-ferroelectric layer and ferroelectric layer-channel layer, then interface protection is provided, but device performance is not optimized
Solution Approach 1:
The patent employs asymmetrical insertion layers where the first insertion layer (between gate electrode and ferroelectric layer) and the second insertion layer (between ferroelectric layer and channel layer) have different thicknesses or material compositions. This asymmetrical configuration is designed to address the different requirements at each interface: the first insertion layer may be thicker to provide better electrical contact and field control with the gate electrode, while the second insertion layer may be optimized for preventing oxygen diffusion into the channel layer. This asymmetric design optimizes both interface protection and overall device performance.
3Reliability
If oxygen migration is prevented by insertion layers, then oxygen defects are reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent optimizes specific parameters of the insertion layers, including thickness (e.g., 1-10 nm range), material composition (such as hafnium oxide, zirconium oxide, or their alloys), and deposition conditions. By carefully controlling these parameters, the insertion layers provide effective oxygen barrier functionality while maintaining compatibility with existing semiconductor manufacturing processes. The thickness and material selection are optimized to achieve the necessary oxygen blocking capability without requiring excessive additional processing steps or specialized equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves the reliability and endurance of ferroelectric memory devices by preventing oxygen defects and maintaining stable performance even under long-term operation up to 1×10^11 cycles.
Implementation Method 1
Incorporation of asymmetrical insertion layers between the gate electrode and ferroelectric layer, and between the ferroelectric layer and channel layer, with the second insertion layer being thinner than the first to prevent oxygen diffusion and maintain electric field control
Implementation Method 2
Ferroelectric memory device includes a ferroelectric material for storing permanent dipole moment. Further, polarity of such dipole moment stored in the ferroelectric material can be switched by adjusting an applied electrical field
Implementation Method 3
polarity of such dipole moment stored in the ferroelectric material can be switched by adjusting an applied electrical field
Implementation Method 4
The polarizations with different polarities stored in the ferroelectric material may affect a threshold voltage of the ferroelectric FET, and can be non-destructively read out by sensing a channel resistance of the ferroelectric FET
Data Source
AI summary
Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.