Semiconductor Layer Layout for Surge Current Heat Control

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Solution Overview

Problem

Power control semiconductor devices, particularly those using silicon carbide, face challenges in withstanding high surge currents due to current concentration issues, leading to potential damage and overheating.

Innovation Solution

The semiconductor device incorporates a surge trigger layer with a higher carrier concentration, strategically located under a metal film, to restrict the flow of surge current within a specific region, reducing current concentration and enhancing heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a semiconductor device uses silicon carbide to achieve higher current density and lower element resistance, then the device performance is improved, but the device becomes more susceptible to damage from surge currents due to current concentration

Engineering Contradiction:
Improvecurrent densityVSAvoidsurge current resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a surge trigger layer with specific carrier concentration (higher than the second conductivity type layer) positioned in a specific region under the metal film. This creates local quality variation where the surge trigger layer has different electrical properties compared to surrounding layers, enabling it to specifically control surge current flow paths while maintaining high current density in other regions for device performance

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If the semiconductor device structure is simplified, then the manufacturing process is easier, but the device cannot effectively restrict surge current flow and dissipate heat

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidsurge current withstanding capability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the semiconductor structure into distinct functional layers including a surge trigger layer, second conductivity type layer, and first conductivity type layer. Each layer has specific doping characteristics and thickness parameters that enable independent optimization of surge protection functionality while maintaining overall manufacturing feasibility through standard semiconductor fabrication processes

Inventive Principle:
Principle #1Segmentation

3Reliability

If the semiconductor device allows high surge current flow, then the device can handle system faults, but current concentration causes overheating and potential damage

Engineering Contradiction:
Improvesurge current handlingVSAvoidheat generation
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The surge trigger layer acts as an intermediary element between the metal film and the underlying semiconductor layers. It mediates the surge current flow by providing a controlled path with specific electrical properties, distributing the current density and preventing direct concentration in critical regions, thereby enabling surge handling while controlling heat generation through controlled resistance

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration significantly increases the device's resistance to surge currents, preventing damage and overheating by limiting current flow and improving heat dissipation.

Implementation Method 1

a surge trigger layer with a higher carrier concentration, strategically located under a metal film, to restrict the flow of surge current within a specific region

Methodology Applied
Scientific EffectCarrier concentration:

Implementation Method 2

enhancing heat dissipation

Methodology Applied
Scientific EffectHeat dissipation: Conduction (thermal)

Data Source

PatentUS20240321862A1Semiconductor device
Publication Date: 2024.09.26 KK TOSHIBA
  • US20240321862A1 patent drawing
  • US20240321862A1 patent drawing
  • US20240321862A1 patent drawing

AI summary

A semiconductor device includes a first electrode, a first semiconductor layer connected to the first electrode, a second semiconductor layer located on a portion of the first semiconductor layer, a third semiconductor layer located on a first portion of the second semiconductor layer, a fourth semiconductor layer located on a second portion of the second semiconductor layer, a fifth semiconductor layer located on a third portion of the second semiconductor layer, a second electrode, a third electrode connected to the third, fourth, and fifth semiconductor layers, and a metal film connected to the third electrode. A length in a second direction of the fifth semiconductor layer is greater than a length in the second direction of the fourth semiconductor layer. The second direction crosses a first direction. The first direction is from the first electrode toward the first semiconductor layer.