Semiconductor Memory Erase Control Using Dual Carrier Injection
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in effectively erasing data without leaving carriers in the charge accumulating film between word lines, which can lead to deteriorated HTDR and NWI characteristics and risk of read failures.
Innovation Solution
The semiconductor memory device employs an erase mode that combines a first erase flow and a second erase flow, where the first flow injects electrons and the second flow injects holes into the charge accumulating film between word lines, ensuring no carriers remain after the erase operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single erase flow is used to erase data in semiconductor memory devices, then the erase operation is simple and fast, but carriers remain in the charge accumulating film between word lines causing deteriorated HTDR and NWI characteristics
Solution Approach 1:
The erase operation is divided into two separate erase flows: a first erase flow that executes a first write operation followed by a first erase operation, and a second erase flow that executes a second write operation followed by a second erase operation. This segmentation allows each flow to target and eliminate different types of carriers (electrons and holes) in the charge accumulating film, ensuring complete carrier removal while maintaining erase efficiency
Solution Approach 2:
The patent applies different voltage conditions in the two erase flows to achieve different erase effects. The first erase flow uses specific voltage combinations to eliminate electrons, while the second erase flow uses different voltage combinations to eliminate holes. By changing the voltage parameters between flows, the system can comprehensively remove all carriers without compromising erase speed
2Manufacturing precision
If carriers remain in the charge accumulating film between word lines after erase, then the erase operation is incomplete, but this leads to read failures and deteriorated memory characteristics
Solution Approach 1:
Each erase flow includes a write operation performed before the erase operation. This preliminary write operation prepares the charge accumulating film by injecting carriers that will subsequently be removed during the erase operation, ensuring complete elimination of all carrier types and achieving thorough data erasure
Solution Approach 2:
The two erase flows are executed sequentially to continuously eliminate different types of carriers. The first erase flow removes electrons, and the second erase flow removes holes, ensuring that no carriers remain in the charge accumulating film. This continuous action guarantees complete erasure without requiring complex additional structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively eliminates carriers between word lines, preventing read failures and maintaining optimal memory cell performance by ensuring accurate data erasure.
Implementation Method 1
the first flow injects electrons and the second flow injects holes into the charge accumulating film between word lines
Implementation Method 2
the first flow injects electrons and the second flow injects holes into the charge accumulating film between word lines
Data Source
AI summary
A semiconductor memory device includes: a memory cell array including a plurality of conductive layers, a semiconductor layer, and charge accumulating sections; and a control circuit that executes an erase operation. The erase operation includes an erase mode that executes a first erase flow. The first erase flow includes: a first write operation in which a first program voltage is applied to the plurality of conductive layers; a first erase operation that is executed after the first write operation, and in which, while a first voltage is applied to a first conductive layer, a voltage higher than the first voltage is applied to the second conductive layer; and a second erase operation that is executed after the first erase operation, and in which, while the first voltage is applied to a second conductive layer, a voltage higher than the first voltage is applied to the first conductive layer.