3D Semiconductor Memory Contact Structure for Higher Integration
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Solution Overview
Problem
Existing two-dimensional semiconductor devices face limitations in integration due to the need for expensive process equipment to achieve finer patterns, which restricts the increase in data storage capacity and performance.
Innovation Solution
A three-dimensional semiconductor memory device is proposed, featuring a cell array structure with multiple stack structures and vertical channel structures, along with a peripheral circuit structure, to enhance integration and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing processes are simpler, but integration is limited by the area occupied by unit memory cells and resolution of fine pattern forming technology
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory structures. Multiple memory cell layers are stacked in the vertical direction, allowing data storage capacity to increase without proportionally increasing the horizontal area. This dimensional change resolves the contradiction by enabling higher integration while maintaining manufacturing feasibility through established semiconductor fabrication processes adapted for 3D structures.
2Quantity of substance
If pattern fineness is increased to improve integration, then data storage capacity increases, but expensive process equipment is needed which sets a practical limitation
Solution Approach 1:
Instead of increasing pattern fineness in the horizontal plane which requires expensive equipment, the patent stacks memory cells vertically to achieve higher capacity. This approach uses conventional fabrication equipment to create 3D structures, avoiding the need for costly extreme ultraviolet lithography or other advanced patterning tools while still achieving high integration.
Solution Approach 2:
Multiple memory cell layers are nested vertically one on top of another, with each layer containing complete memory cell structures including transistors and storage elements. This nesting approach maximizes storage capacity within the available vertical space without requiring finer horizontal patterning, thus avoiding expensive process equipment.
3Quantity of substance
If three-dimensional stacked structures are implemented, then data storage capacity per unit area increases, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into modular stages: forming individual memory cell layers with complete transistor and storage structures, then stacking multiple such layers vertically. Each layer can be fabricated using standard processes, and the stacking is achieved through controlled deposition and etching steps. This segmentation reduces overall process complexity compared to attempting to create all structures in a single complex planar layout.
Solution Approach 2:
The patent implements 3D vertical stacking of memory cell layers, where each layer is a complete functional memory unit. This vertical arrangement achieves high storage capacity per unit area by utilizing the third dimension (height) rather than expanding horizontally. The manufacturing complexity is managed by using sequential deposition and etching processes that build structures layer-by-layer in the vertical direction.
Data Source
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AI summary
A semiconductor memory device including a cell array structure (CS) and a peripheral circuit structure (PS) is provided. The cell array structure includes a first stack structure (ST1), a second stack structure (ST2) on the first stack structure, and a third stack structure (ST3) on the second stack structure, each of the first to third stack structures including a plurality of word lines (EL1, EL2, EL3), vertical channel structures (VS) extending into the first to third stack structures, and a second cell contact plug (CP2a, CP2b) extending into the first to third stack structures and connected to a second contact plug at an end of a second word line in the second stack structure. The second cell contact plug includes a first horizontal protrusion (LP1, LP2) having a horizontal width that increases discontinuously at a connection portion of the first stack structure and the second stack structure.