Multilayer Cross Point Memory With Hierarchical Bit Line Switching
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Solution Overview
Problem
Nonvolatile memory devices with variable resistance elements face a challenge in reducing leak current of non-selected memory cells in cross point structures, particularly with bidirectional elements, where active leak current reduction methods are unavailable, leading to increased array size and layout area.
Innovation Solution
A multilayer cross point structure with a hierarchical bit line scheme is adopted, using selection switch elements to control electrical connections between global bit lines and common-connected bit lines in even and odd layers, reducing array size without increasing layout area and minimizing leak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the array unit is made as large as possible to reduce chip area, then the area of peripheral circuits is reduced, but the leak current of non-selected memory cells increases
Solution Approach 1:
The memory cell array is divided into multiple array units, each with its own selection switch elements. This segmentation allows independent control of leak current in each unit while maintaining a compact overall structure. The selection switch elements can selectively activate only the required array unit, reducing leak current from non-selected units.
Solution Approach 2:
Selection switch elements are introduced as intermediary components between the bit lines and memory cells. These switch elements act as mediators that control current flow, enabling selective activation of memory cells and reduction of leak current from non-selected cells while maintaining array functionality.
2Object-generated harmful factors
If the array unit is made as small as possible to reduce leak current, then the leak current of non-selected memory cells is reduced, but the chip area increases due to larger peripheral circuits
Solution Approach 1:
The selection switch elements serve multiple functions: they act as leak current reduction mechanisms for non-selected memory cells, serve as address decoding components, and enable selective activation of array units. This multi-functionality reduces the need for separate peripheral circuits, thereby reducing overall chip area despite smaller array units.
Solution Approach 2:
The selection switch elements combine the functions of address decoding and memory cell selection into a single component structure. This merging of functions eliminates the need for separate decoding circuits and selection mechanisms, reducing peripheral circuit area and offsetting the area increase from smaller array units.
3Adaptability or versatility
If bidirectional variable resistance elements are used to enable bidirectional resistance change, then memory operation flexibility is improved, but active leak current reduction methods become unavailable
Solution Approach 1:
Selection switch elements are introduced as intermediary components that enable active control of current flow to bidirectional variable resistance elements. These switch elements mediate between the control circuitry and the bidirectional elements, providing the necessary current direction control and leak current reduction that bidirectional elements alone cannot achieve.
Solution Approach 2:
The selection switch elements provide dynamic control over current flow direction and magnitude to the bidirectional variable resistance elements. This dynamic control enables adaptive leak current reduction while maintaining the bidirectional operation flexibility, as the switches can adjust their state based on read/write operations or standby conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a small layout area with reduced leak current of non-selected memory cells, enabling efficient operation and integration of memory cell arrays.
Implementation Method 1
a variable resistance element whose resistance value reversibly changes according to an electrical signal
Implementation Method 2
the first selection switch element controls switching of electrical connection/non-connection between the global bit line for the relevant basic array plane and common-connected even layer bit lines
Data Source
AI summary
Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements (101 to 104) controls switching of electrical connection/non-connection between the common-connected even layer bit line and a global bit line (GBL), and each of selection switch elements (111 to 114) control switching of connection/non-connection between the common-connected odd layer bit line and the global bit line (GBL).