Doping Edge Channel Layers for Uniform 3D Memory Programming
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Solution Overview
Problem
In 3D stacked non-volatile memory devices, programming and erase speed variations occur due to varying thickness of blocking oxide layers, leading to increased programming time and read disturb issues, as the thickness of these layers differs based on the distance from local interconnects.
Innovation Solution
Doping channel layers in memory strings close to local interconnects while keeping those farther away undoped or less doped, to uniformize program speed and reduce read disturb, achieved through methods like carrier gas enrichment, doped spin-on glass deposition, or plasma doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If blocking oxide layer thickness is reduced to improve programming speed, then programming speed increases, but read disturb increases
Solution Approach 1:
The patent applies different doping conditions to channel layers at different locations within the memory device. Specifically, channel layers closer to local interconnects receive different doping treatment than those farther away, creating local variations in threshold voltage that compensate for the varying blocking oxide thickness and achieve uniform programming speed across the device while maintaining read disturb performance
2Ease of manufacture
If blocking oxide layer thickness varies to simplify manufacturing, then manufacturing complexity reduces, but programming speed uniformity deteriorates
Solution Approach 1:
The patent changes the doping parameter (dopant concentration) of channel layers based on their location relative to local interconnects. By adjusting the doping level, the threshold voltage of memory cells is modified to compensate for variations in blocking oxide thickness, thereby achieving uniform programming speed without requiring precise control of the blocking oxide layer thickness during manufacturing
3Manufacturing precision
If channel layers are doped to uniformize programming speed, then programming speed uniformity improves, but device complexity increases
Solution Approach 1:
The patent segments the memory device into different regions based on distance from local interconnects, and applies different doping treatments to each segment. This segmentation approach allows for targeted doping of specific channel layers that require threshold voltage adjustment, rather than uniformly doping all channel layers, thereby reducing the overall complexity of the doping process while achieving programming speed uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming speed uniformity and reduces read disturb by adjusting the intrinsic threshold voltage of memory cells, thereby improving overall memory device performance and reliability.
Implementation Method 1
Doping channel layers of memory strings in a first edge region of the stack... The doping modifies an intrinsic threshold voltage of the memory cells
Implementation Method 2
achieved through methods like carrier gas enrichment
Implementation Method 3
achieved through methods like carrier gas enrichment, doped spin-on glass deposition, or plasma doping
Data Source
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AI summary
A three-dimensional stacked memory device provides uniform programming speeds for a block of memory cells. The channel layers of the memory strings which are relatively close to a local interconnect of a stack are doped to account for a reduced blocking oxide thickness. Channel layers of remaining memory strings are undoped. The doping can be performing by masking the channel layers which are to remain undoped while exposing the other memory holes to a dopant. The dopant can be provided, e.g., in a carrier gas, spin on glass or other solid, or by plasma doping. An n-type dopant such as antimony, arsenic or phosphorus may be used. Heating causes the dopants to diffuse into the channel layer. Another approach deposits doped silicon for some of the channel layers and undoped silicon for other channel layers.