TFT Active Layer Layout for Lower Resistance and Capacitance
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Solution Overview
Problem
The formation of the active layer in thin-film transistors (TFTs) of liquid-crystal displays (LCDs) hinders achieving better display quality due to high resistance and limited electrical performance.
Innovation Solution
The active layer pattern design is optimized by making the non-channel regions wider than the channel regions, with a specific width configuration that reduces the overall resistance and enhances electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the active layer is designed with conventional uniform width, then the manufacturing process is simple, but the resistance is high and electrical performance is limited
Solution Approach 1:
The active layer is designed with different widths in different regions: wider in non-channel regions to reduce resistance and parasitic capacitance, and narrower in channel regions to maintain transistor performance. This local variation in geometry optimizes electrical characteristics without requiring material or process changes.
Solution Approach 2:
The patent changes the geometric parameter (width) of the active layer along its length. By varying the width parameter from uniform to non-uniform, with specific wider sections at the ends and narrower sections in the middle, the resistance and parasitic capacitance are reduced while maintaining the transistor's channel function.
2Reliability
If the active layer width is increased to reduce resistance, then the electrical performance improves, but the parasitic capacitance increases
Solution Approach 1:
The active layer width is locally increased only in the non-channel regions where resistance reduction is needed, while the channel region width is kept narrower. This localized approach reduces the overall parasitic capacitance compared to a uniformly wide active layer, while still achieving the resistance reduction benefit in the contact regions.
Data Source
AI summary
An electronic panel includes a first substrate; a conductive line disposed on the first substrate and extending along a first direction; a conductive element extending along a second direction perpendicular to the first direction; and an active layer disposed between the conductive element and the first substrate. In a top view, the active layer includes a first overlapping region overlapping a portion of the conductive line; a first contact region electrically connected to a connecting portion of the conductive element through a first via hole; and a turning region between the first overlapping region and the first contact region. The turning region doesn't extend along the first direction and the second direction.