Active Matrix Substrate Layout for Gate Line Capacitance Balancing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing display devices with non-rectangular substrates face issues due to the difference in capacitance between first and second gate lines, leading to waveform differences in gate signals and subsequent luminance differences, which deteriorate the display quality.
Innovation Solution
The display device incorporates a substrate with a notch or aperture, featuring gate lines that bypass the notch, and electrodes with capacitor forming portions in the pixel region and first gate line interposed portions in the pixel adjacent region, which overlap with the gate lines to compensate for capacitance differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If the first gate lines bypass the notch in the non-active area, then the display device can achieve a non-rectangular shape, but the distance between portions of the first gate lines in the non-active area becomes smaller than the distance between portions in the active area, making it impossible to form sufficient polysilicon layer for capacitance compensation
Solution Approach 1:
The patent divides the capacitance compensation structure into two distinct parts: (1) a capacitor forming portion in the active area using polysilicon layer, and (2) a first gate line interposed portion in the non-active area using electrode layer and source line layer. This segmentation allows each part to be optimized for its specific function and location constraints.
Solution Approach 2:
The patent utilizes the vertical stacking of layers (electrode layer, gate line layer, source line layer) to create capacitance compensation structures. By forming capacitor forming portions and first gate line interposed portions in different layers that overlap when viewed in plan view, the patent compensates for capacitance differences without requiring additional horizontal space in the constrained non-active area.
2Device complexity
If the polysilicon layer is formed in the non-active area with reduced gate line spacing, then the device structure is simplified, but the size of polysilicon layer per gate line becomes insufficient, failing to reduce capacitance difference between first and second gate lines
Solution Approach 1:
The patent applies different capacitance compensation mechanisms to different regions: the capacitor forming portion in the active area provides primary capacitance compensation, while the first gate line interposed portion in the non-active area provides additional compensation specifically for first gate lines. This local differentiation ensures each region receives appropriate capacitance compensation despite structural constraints.
Solution Approach 2:
The patent creates a composite capacitance compensation structure combining polysilicon material (in capacitor forming portion) with conductive layer materials (electrode layer and source line layer in first gate line interposed portion). This composite approach leverages the electrical properties of different materials to achieve sufficient capacitance compensation in both active and non-active areas.
3Ease of manufacture
If the capacitance difference between first and second gate lines is not sufficiently reduced, then the manufacturing process is simplified, but waveform differences in gate signals occur, leading to luminance differences and deteriorated display quality
Solution Approach 1:
The patent preemptively compensates for capacitance differences between first and second gate lines by incorporating both capacitor forming portions and first gate line interposed portions before signal transmission occurs. This preliminary capacitance equalization prevents waveform differences and subsequent luminance non-uniformity in the display output.
Solution Approach 2:
The patent designs the capacitance compensation structures with specific geometric parameters (areas of capacitor forming portions, dimensions and positions of first gate line interposed portions) that are determined based on the capacitance characteristics of the gate lines. This feedback-based design ensures the compensation structures provide the precise capacitance values needed to equalize gate line performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the formation of large capacitors between the electrodes and the gate lines, effectively reducing the capacitance differences between first and second gate lines, thereby preventing display quality deterioration due to waveform and luminance differences.
Implementation Method 1
each electrode include at least either of a capacitor forming portion that is arranged within the pixel region and overlaps with at least one of the first gate line when viewed in a plan view, and a first gate line interposed portion that is arranged in the pixel adjacent region and includes an electrode layer portion formed in the electrode layer and a source line layer portion formed in the source line layer; and the electrode layer portion and the source line layer portion overlap with at least one of the first gate lines in the pixel adjacent region when viewed in a plan view
Data Source
AI summary
An active matrix substrate includes a substrate in which a notch or an aperture is formed, and electrodes. Each electrode includes at least either of: a capacitor forming portion that is arranged in a region other than a bypass region and overlaps with at least one of a plurality of bypass gate lines when viewed in a plan view; and an electrode layer portion that is formed in an electrode layer and that composes a bypass gate line interposed portion together with a source line layer portion formed in a source line layer in the bypass region. The electrode layer portion and the source line layer portion overlap with at least one of the bypass gate lines in the bypass region when viewed in a plan view, and at least one of the bypass gate lines is positioned between the electrode layer portion and the source line layer portion in a normal line direction of the substrate.