Floating Gate Extension for NVM Cell Scaling
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Solution Overview
Problem
Reducing the size of floating-gate non-volatile memory (NVM) cells while maintaining reliability and preventing breakdown risks due to reduced breakdown voltages caused by smaller feature sizes, which existing solutions attempt to address by using high-resolution lithography tools that increase complexity and cost.
Innovation Solution
Forming extended floating gate regions using a spacer etch to create sub-lithographic features, increasing the distance between the control gate and doped well regions, thereby reducing breakdown risks without requiring high-resolution lithography tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If floating gate dimensions are reduced to shrink cell array size, then device size is reduced, but breakdown voltage decreases leading to reliability degradation
Solution Approach 1:
The patent extends the floating gate laterally beyond the channel region into adjacent areas, adding dimensional extension in the lateral direction. This creates extended floating gate regions that increase the distance between the control gate and doped well regions, thereby maintaining breakdown voltage while allowing the channel dimensions to be scaled down for smaller cell size.
Solution Approach 2:
The patent forms the extended floating gate regions before forming the control gate layer. By preliminarily extending the floating gate structure and positioning it relative to the doped well regions, the design ensures adequate spacing is established before subsequent processing steps, preventing breakdown issues in advance.
2Ease of manufacture
If conventional lithography is used to pattern floating gates, then manufacturing is simpler, but feature size cannot be reduced below lithographic limits
Solution Approach 1:
The patent performs preliminary patterning of the floating gate to define the channel region, then extends the floating gate material beyond the patterned channels before forming the control gate. This preliminary extension step allows the final floating gate structure to have dimensions smaller than what could be directly patterned by lithography, achieving sub-lithographic precision.
Solution Approach 2:
The patent separates the floating gate formation into distinct stages: initial patterning for channel definition, then extension to create sub-lithographic features. This segmentation allows conventional lithography to handle the main patterning while subsequent processing achieves finer dimensional control.
Data Source
AI summary
Methods are disclosed for extending floating gate regions within floating gate cells to form sub-lithographic features. Related floating gate cells and non-volatile memory (NVM) systems are also disclosed. In part, the disclosed embodiments utilize a spacer etch to form extended floating gate regions and floating gate slits with sub-lithographic dimensions thereby achieving desired increased spacing between control gate layers and doped regions underlying floating gate structures while still allowing for reductions in the overall size of floating-gate NVM cells. These advantageous results are achieved in part by depositing an additional floating gate layer over previously formed floating gate regions and then using the spacer etch to form the extended floating gate regions as sidewall structures and sub-lithographic floating gate slits. The resulting floating gate structures reduce breakdown down risks, thereby improving device reliability.