Three Terminal Isolation Elements for 3D Memory Arrays
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Solution Overview
Problem
As semiconductor memory technologies scale down, they face challenges such as increased variability in memory cell I-V characteristics, reduced memory cell sensing currents, and increased bit line settling times, which affect the performance and efficiency of non-volatile memory devices.
Innovation Solution
A monolithic three-dimensional memory array is developed, featuring global bit lines, vertically-oriented bit lines, word lines, memory cells coupled between the bit lines and word lines, and isolation elements that include a vertical thin-film transistor coupled in series with a threshold selector device to reduce leakage currents and improve memory cell operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If process geometries are shrunk to reduce cost per bit, then manufacturing cost decreases, but variability in memory cell I-V characteristics increases
Solution Approach 1:
A selector device is introduced as an intermediary component between the memory cell and the bit line. This selector device acts as a gatekeeper that controls current flow, allowing precise measurement of memory cell characteristics while blocking leakage currents. The selector device enables accurate sensing of small sensing currents even in scaled-down geometries by providing a high OFF-state current ratio, thus maintaining reliability while enabling cost reduction through scaling.
2Loss of energy
If process geometries are shrunk to reduce cost per bit, then manufacturing cost decreases, but memory cell sensing currents are reduced
Solution Approach 1:
The selector device serves as a current amplification intermediary. By providing a low ON-resistance path when selected and blocking leakage when unselected, it enables the sensing circuitry to detect extremely small sensing currents from scaled-down memory cells. The high OFF-state current ratio of the selector device ensures that leakage currents do not mask the small sensing currents, allowing continued operation at reduced geometries with lower sensing currents.
3Loss of energy
If process geometries are shrunk to reduce cost per bit, then manufacturing cost decreases, but bit line settling times increase
Solution Approach 1:
The selector device acts as a signal isolation intermediary that prevents leakage currents from unselected memory cells from contaminating the bit line. By blocking these parasitic currents, the selector device enables faster settling of the bit line voltage to its final value, reducing the settling time even as memory cell dimensions are reduced and capacitances are lowered.
4Reliability
If isolation elements are added to reduce leakage currents, then memory cell operation improves, but device complexity increases
Solution Approach 1:
The selector device merges multiple functions into a single component: it provides leakage current blocking, enables sensing of small currents, and facilitates controlled current flow during read and program operations. By combining these isolation and control functions into one integrated device rather than using separate isolation elements, the patent reduces overall device complexity while achieving improved memory cell operation and reduced leakage currents.
Data Source
AI summary
A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of isolation elements coupled between the vertically-oriented bit lines and the global bit lines. Each isolation element includes a vertical thin-film transistor and a threshold selector device.