DRAM Bit Line Sacrificial Layers for Residue-Free Capacitor Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing depth-to-width ratio of dielectric and capacitor contact holes between adjacent bit line structures in DRAMs leads to etching residues, causing communication between capacitor contact holes and affecting semiconductor structure yield.
Innovation Solution
A method involving discrete bit line structures with a first sacrificial layer of one material and a second sacrificial layer of another material, where the layers are patterned and removed to form openings and capacitor contact holes, ensuring alternate arrangement and reducing etching residue issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the line width of DRAMs decreases to increase integration density, then the distance between adjacent bit line structures decreases, but the depth-to-width ratio of dielectric layer and capacitor contact holes increases, leading to etching residues
Solution Approach 1:
The sacrificial layer is divided into multiple segments (first sacrificial layer 201, second sacrificial layer 202, and third sacrificial layer 203) with different materials and thicknesses. This segmentation allows selective removal of portions of the sacrificial layer, enabling complete clearance of etching residues while maintaining the required depth-to-width ratio for high integration density.
Solution Approach 2:
The first sacrificial layer 201 is formed preliminarily at the bottom of the gap before forming the second and third sacrificial layers. This preliminary action ensures that the bottom portion is prepared in advance, allowing subsequent etching processes to completely remove all sacrificial material without leaving residues, thus solving the etching residue problem while maintaining high integration density.
2Reliability
If secondary etching is performed to remove etching residues, then the trenches become larger in size, but the size of subsequently formed capacitor contact holes is affected
Solution Approach 1:
Different portions of the sacrificial layer are assigned different materials and thicknesses: the first sacrificial layer 201 at the bottom has different properties than the second sacrificial layer 202 and third sacrificial layer 203. This local quality differentiation enables selective etching where the first sacrificial layer is completely removed to eliminate residues, while the second and third layers remain to define the precise capacitor contact hole dimensions, thus maintaining both yield and manufacturing precision.
Solution Approach 2:
The first sacrificial layer 201 acts as an intermediary that is completely removed during etching to ensure no residues remain, while the second sacrificial layer 202 and third sacrificial layer 203 serve as intermediaries that define the final capacitor contact hole size. This multi-layer intermediary approach allows complete residue removal without affecting the precision of the final structure dimensions.
3Device complexity
If a single-layer sacrificial structure is used, then the process is simpler, but etching residues remain in the bottom sacrificial layer due to large depth-to-width ratio
Solution Approach 1:
The single-layer sacrificial structure is segmented into multiple layers (first sacrificial layer 201, second sacrificial layer 202, third sacrificial layer 203) with different materials and thicknesses. This segmentation enables complete etching removal of the bottom portion (first sacrificial layer) while maintaining structural integrity, thus improving etching completeness without excessive complexity increase.
Solution Approach 2:
The sacrificial layer structure uses composite materials with different etch selectivities: the first sacrificial layer 201 uses a material that is completely removable, while the second sacrificial layer 202 and third sacrificial layer 203 use materials that provide structural support. This composite material approach ensures complete etching removal where needed while maintaining structural integrity, resolving the contradiction between simplicity and etching completeness.
Data Source
AI summary
The present disclosure provides a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure includes: providing a substrate, and forming discrete bit line structures on the substrate; forming a first sacrificial layer on the surface of the substrate on the bottoms of gaps of the bit line structures; forming a second sacrificial layer filling the gaps of the discrete bit line structures; patterning the second sacrificial layer and the first sacrificial layer to form openings, the formed openings and the remaining of the second sacrificial layer being arranged alternately in an extension direction of the bit line structures; forming a dielectric layer filling the openings; and, removing the remaining of the first sacrificial layer and the remaining of the second sacrificial layer to form capacitor contact holes, the formed capacitor contact holes and the dielectric layer being arranged alternately.