Buried Line Stack Fabrication Through Top-Layer Via Channeling
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Solution Overview
Problem
Existing fabrication techniques for buried lines in electronic devices, such as integrated circuits and memory devices, are inefficient due to the high number of processing steps and increased fabrication costs, as they require constructing buried lines before forming layers above them.
Innovation Solution
The described techniques involve patterning vias at the top layer to create channels in buried layers, filling these channels with conductive material, and using the same vias to form additional channels within the conductive material, allowing for simultaneous construction of buried lines at multiple layers, including in 3D memory devices with a cross-point architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional fabrication techniques are used to form buried lines at multiple layers, then each layer can be constructed individually, but the number of processing steps and fabrication time increase significantly
Solution Approach 1:
The patent combines the formation of buried lines at multiple layers into a single integrated process. A composite stack is formed with multiple layers, and a single set of masking and etching operations simultaneously defines buried lines at multiple depths. This merging of operations eliminates the need for separate processing sequences for each layer, directly resolving the contradiction between manufacturing precision and fabrication productivity.
Solution Approach 2:
The patent performs preliminary actions by forming the complete composite stack structure before defining the buried lines. The stack of alternating conductive and dielectric layers is prepared in advance, and then a single masking pattern is applied that pre-determines the locations of buried lines at multiple layers. This preliminary structuring enables subsequent single-step processing to achieve multi-layer buried line formation, improving throughput while maintaining precision.
2Reliability
If multiple processing steps are used to form buried lines at each layer separately, then layer-by-layer construction is achieved, but fabrication costs increase
Solution Approach 1:
The patent merges multiple fabrication operations into a single integrated process sequence. Instead of performing separate deposition, masking, and etching steps for each layer, the method uses one composite masking step and one etching step to simultaneously create buried lines at multiple layers. This consolidation reduces the total number of processing steps, lowering fabrication costs while maintaining construction reliability through the unified process approach.
Solution Approach 2:
The patent employs a universal masking pattern that serves multiple functions simultaneously. The single masking layer defines the geometry of buried lines at all levels of the composite stack, making the masking operation multi-functional. This universal approach eliminates the need for layer-specific masking designs and reduces the overall complexity of the fabrication process, thereby reducing costs while ensuring reliable buried line formation.
3Ease of operation
If buried lines are formed before subsequent layers are deposited, then the buried layer is accessible for processing, but the number of processing steps increases
Solution Approach 1:
The patent inverts the conventional sequence of operations. Instead of forming buried lines first and then depositing subsequent layers, the method deposits the complete composite stack of alternating conductive and dielectric layers first, and then forms the buried lines in a subsequent step. This inversion allows the buried lines to be defined after the stack structure is complete, enabling a single masking and etching operation to affect multiple layers simultaneously, thereby reducing process complexity while maintaining accessibility for processing.
Data Source
AI summary
Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.