Display Device Transistor Source Electrode Asymmetry

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Display devices with liquid crystal technology suffer from systematic errors in parasitic capacitance due to manufacturing errors, leading to irregularities in pixel voltage and abnormal displays, such as stripe irregularity, caused by variations in the overlap area between the gate and source electrodes of transistors.

Innovation Solution

The design includes specific configurations for the source and drain electrodes of transistors in pixel circuits, where the source electrodes of even and odd transistors are stretched in predetermined directions to overlap with the gate electrodes, and the drain electrodes are positioned to overlap with the gate electrodes in reverse directions, thereby stabilizing the parasitic capacitance and reducing systematic errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the source electrodes of even and odd transistors are stretched in predetermined directions to overlap with gate electrodes, then the parasitic capacitance variation is suppressed and display quality is improved, but the manufacturing complexity increases due to precise alignment requirements

Engineering Contradiction:
Improvedisplay qualityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source electrodes of even-numbered and odd-numbered transistors are intentionally designed with asymmetric stretching directions. Even transistor source electrodes stretch in one direction while odd transistor source electrodes stretch in the opposite direction, creating a symmetric pattern of asymmetry that balances parasitic capacitance across all pixels

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

Different stretching directions are applied to source electrodes based on their local position (even vs odd transistor locations). This local differentiation in electrode orientation allows each transistor to have optimized parasitic capacitance characteristics suited to its specific position in the pixel array

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If two scanning signal lines are disposed for each row with alternating connections, then the space utilization in the frame area is improved, but the number of scanning signal lines increases leading to higher complexity

Engineering Contradiction:
Improveframe area utilizationVSAvoidnumber of scanning signal lines
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The scanning signal lines are segmented into two separate lines (first and second scanning signal lines) that alternately connect to even and odd transistors respectively. This segmentation allows more efficient space utilization while distributing the connection complexity across multiple lines

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each scanning signal line serves multiple functions by alternating connections to different transistors. The first scanning signal line connects to even transistors while the second connects to odd transistors, allowing the system to achieve comprehensive coverage with fewer total lines than a direct one-to-one connection would require

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8378350B2Display device
Publication Date: 2013.02.19 PANASONIC INTELLECTUAL PROPERTY CORP OF AMERICA
  • US8378350B2 patent drawing
  • US8378350B2 patent drawing
  • US8378350B2 patent drawing

AI summary

Provided is a display device including first and second gate interconnections; a first pixel circuit disposed at one side of the first gate interconnection, the first pixel circuit including a first transistor, a gate electrode of the first transistor electrically connected to the first gate interconnection, a source electrode of the first transistor formed in a source layer, the source electrode including a first source electrode facing portion overlapping with the gate electrode; and a second pixel circuit disposed at the other side of the second gate interconnection, the second pixel circuit including a second transistor, a gate electrode of the second transistor electrically connected to the second gate interconnection, a source electrode of the second transistor formed in the source layer, the source electrode including a second source electrode facing portion overlapping with the gate electrode and stretched along the first source electrode facing portion.