Cross-Tier Word Line Layout to Reduce Memory Cell Coupling

Solution Overview

Problem

As semiconductor memory devices shrink in size, the reduced pitch between memory cells leads to increased coupling effects between word lines, resulting in reduced word line speed and integrated circuit performance.

Innovation Solution

The memory device incorporates a memory cell array with word lines on odd-numbered tiers oriented differently from those on even-numbered tiers, reducing cell-to-cell spacing and minimizing the coupling effect between stacked tiers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the pitch between memory cells is reduced to shrink device size, then the device size is minimized, but the coupling effect between word lines increases

Engineering Contradiction:

Improvedevice sizeVSAvoidcoupling effect

Core Design Contradiction:

Volume of moving objectVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry by orienting word lines on odd-numbered tiers in a first direction and word lines on even-numbered tiers in a second direction that is angularly offset from the first direction. This asymmetric angular offset breaks the symmetry of the stacked tiers, increasing the spacing between word lines on adjacent tiers and thereby reducing the capacitive coupling effect between them while maintaining the reduced pitch for miniaturization.

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

The patent introduces a new dimensional parameter by adding angular orientation as a degree of freedom for word line arrangement. Instead of only varying the spatial position or pitch, the invention rotates word lines between odd and even tiers, utilizing the angular dimension to increase effective spacing and reduce coupling while maintaining the compact vertical stack structure.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If the pitch between memory cells is reduced to shrink device size, then the device size is minimized, but the word line speed is reduced

Engineering Contradiction:

Improvedevice sizeVSAvoidword line speed

Core Design Contradiction:

Volume of moving objectVSSpeed

Solution Approach 1:

The asymmetric angular offset between word lines on odd and even tiers reduces the capacitive coupling effect, which in turn reduces the signal delay and improves word line propagation speed. This allows the device to maintain minimal size through reduced pitch while simultaneously improving word line speed by minimizing the harmful coupling effect through directional asymmetry.

Inventive Principle:

Principle #4Asymmetry

3Length of stationary object

If the spacing between stacked tiers is reduced to maintain minimal size, then the device size is minimized, but the coupling effect between word lines increases

Engineering Contradiction:

Improvetier spacingVSAvoidcoupling effect

Core Design Contradiction:

Length of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry by orienting word lines on odd-numbered tiers in a first direction and word lines on even-numbered tiers in a second direction that is angularly offset from the first direction. This asymmetric angular offset breaks the symmetry of the stacked tiers, increasing the spacing between word lines on adjacent tiers and thereby reducing the capacitive coupling effect between them while maintaining the reduced pitch for miniaturization.

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentUS12217817B2Memory device and method of forming the same

Publication Date: 2025.02.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.