Polysilicon Gate Structure to Suppress Kink Effects and GIDL
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Solution Overview
Problem
In semiconductor manufacturing, the thinner gate insulation layer at the edge regions of transistors leads to kink effects and gate-induced drain leakage (GIDL), especially in smaller transistors operating at medium voltage (MV) or high voltage (HV), affecting their performance and reliability.
Innovation Solution
The transistor structure incorporates polysilicon layers with specific opening patterns at the edge regions to expose the gate insulation layer, increasing the threshold voltage and reducing kink effects and GIDL by maintaining the gate insulation layer thickness at 70% or less of the center region's thickness, and using dielectric spacers to cover the openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate insulation layer thickness is reduced to improve transistor switching speed and reduce capacitance, then the transistor operates faster, but kink effects and GIDL occur at edge regions due to non-uniform thickness
Solution Approach 1:
The patent applies local quality by creating non-uniform gate insulation layer thickness across different regions of the transistor. The edge regions have thinner gate insulation (70% or less of center thickness) to reduce capacitance and improve switching speed, while the center region maintains sufficient thickness to prevent kink effects and GIDL. This spatial variation in insulation thickness allows simultaneous optimization of speed and reliability.
Solution Approach 2:
The gate insulation layer is segmented into distinct thickness zones: edge regions with reduced thickness and a center region with full thickness. This segmentation is achieved through selective removal processes that pattern the insulation layer, creating discrete functional zones that address different performance requirements independently.
2Reliability
If the gate insulation layer thickness is made uniform across the transistor to eliminate kink effects and GIDL, then reliability improves, but transistor switching speed decreases due to increased capacitance
Solution Approach 1:
Rather than using uniform thickness, the patent implements local quality variations where the gate insulation layer has different thicknesses at different locations. The thinner edge regions reduce capacitance for faster switching, while the thicker center region ensures reliability. This localized differentiation resolves the contradiction by allowing each region to be optimized for its specific function.
3Productivity
If the transistor size is reduced to increase integration density, then productivity improves, but kink effects and GIDL become more significant due to edge region dominance
Solution Approach 1:
In smaller transistors, edge regions constitute a larger proportion of the total area, making kink effects and GIDL more significant. The patent addresses this by applying local quality control through selective thinning of the gate insulation at edges, which reduces the harmful effects in these dominant edge regions while maintaining overall transistor functionality and enabling higher integration density.
Solution Approach 2:
The patent applies preliminary anti-action by proactively modifying the gate insulation layer structure before the transistor operates. The selective thinning process pre-compensates for the kink effects and GIDL that would otherwise occur during operation, preventing these harmful effects before they can degrade transistor performance in scaled devices.
Data Source
AI summary
A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.