CMOS Image Sensor Package Layout for Thin High-Integration Modules
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing package structures for CMOS image sensor chips are large and bulky, leading to a low yield and poor integration due to the need for extensive wiring and routing, which hinders the development of thin and light electronic devices.
Innovation Solution
A package structure featuring a light-transmitting substrate with a thin wiring layer and a photosensitive chip, where the first metal wire does not overlap the photosensitive region, allowing for direct electrical connection and encapsulation, reducing the overall thickness and increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a conventional package structure with extensive wiring and routing is used, then electrical connection is achieved, but the package size becomes large and bulky
Solution Approach 1:
The patent transitions from planar wiring on a substrate to three-dimensional vertical stacking, where the photosensitive chip is positioned directly above the light-transmitting substrate with conductors extending vertically. This dimensional change eliminates the need for extensive lateral routing while achieving the same electrical connections, thereby reducing package thickness without sacrificing connectivity.
Solution Approach 2:
The patent implements nesting by placing the photosensitive chip, active chip, and conductors within the vertical space above the light-transmitting substrate, encapsulating them together in a compact configuration. This nested arrangement integrates multiple components into a single vertical column, eliminating the need for separate wiring layers and reducing overall package complexity.
2Reliability
If extensive wiring and routing are implemented in a plastic or ceramic substrate, then electrical connection is achieved, but manufacturing yield decreases
Solution Approach 1:
The patent extracts the wiring function from the traditional plastic or ceramic substrate and relocates it to vertical conductors that extend directly from the light-transmitting substrate to the photosensitive chip. This extraction eliminates the complex substrate routing layer, simplifying the manufacturing process and improving yield by removing a potential source of defects.
Solution Approach 2:
The patent changes the geometric parameters of the wiring structure from two-dimensional planar traces to one-dimensional vertical conductors. This parameter change reduces the number of wiring intersections and routing complexity, thereby improving manufacturing reliability and yield while maintaining electrical connectivity.
3Illumination intensity
If the photosensitive region overlaps with metal wires, then electrical connection is achieved, but light penetration is blocked
Solution Approach 1:
The patent resolves the overlap issue by transitioning from horizontal wire routing to vertical conductor placement. The conductors are positioned at the periphery or edges of the photosensitive chip, allowing light to pass through the central photosensitive region unobstructed while maintaining electrical connection through the vertical conductors that connect to contact pads on the chip edges.
Solution Approach 2:
The patent applies local quality by differentiating the functional zones: the central region of the photosensitive chip is optimized for light reception with no overlapping conductors, while the peripheral regions contain the conductors and contact pads for electrical connection. This spatial differentiation ensures both optimal light penetration and electrical connectivity without compromise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution results in a thinner, more integrated package structure with improved light penetration and reduced manufacturing complexity, addressing the issues of bulkiness and low yield in existing technologies.
Implementation Method 1
a photosensitive chip (5) electrically connected to the first metal wire, the photosensitive chip including a photosensitive surface (11) configured to sense a light signal
Implementation Method 2
a light-transmitting substrate (2), a wiring layer (3) located on a first side of the light-transmitting substrate (2)
Data Source
AI summary
The present disclosure provides chip package structure, packaging method, camera module and electronic equipment. The package structure includes chip package module, which includes light-transmitting substrate, wiring layer located on side of light-transmitting substrate and including first metal wire, conductor located on side of wiring layer facing away from light-transmitting substrate, photosensitive chip located on side of wiring layer facing away from the light-transmitting substrate, active chip located on side of wiring layer facing away from light-transmitting substrate, and plastic encapsulation layer encapsulating photosensitive chip and active chip. The conductor includes first end electrically connected to first metal wire, and second end. The photosensitive chip includes pin electrically connected to first metal wire and has photosensitive surface facing towards light-transmitting substrate. The photosensitive surface includes photosensitive region that is not overlapping first metal wire. The active chip includes pin electrically connected to first metal wire.